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MichaelJSrMichaelJSr
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Merge pull request vortexgpgpu#228 from MichaelJSr/simx-vpu
Added compile options for riscv vector extension and option to generate new riscv vector tests
2 parents 403f7da + 91429e6 commit c841745

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16 files changed

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‎.github/workflows/ci.yml‎

Lines changed: 56 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -117,7 +117,62 @@ jobs:
117117
strategy:
118118
fail-fast: false
119119
matrix:
120-
name: [regression, opencl, cache, config1, config2, debug, scope, stress, synthesis, vm, vector]
120+
name: [regression, opencl, cache, config1, config2, debug, scope, stress, synthesis, vm]
121+
xlen: [32, 64]
122+
123+
steps:
124+
- name: Checkout code
125+
uses: actions/checkout@v2
126+
127+
- name: Install Dependencies
128+
run: |
129+
sudo bash ./ci/install_dependencies.sh
130+
131+
- name: Cache Toolchain Directory
132+
id: cache-toolchain
133+
uses: actions/cache@v4
134+
with:
135+
path: tools
136+
key: ${{ runner.os }}-toolchain-v0.1
137+
restore-keys: |
138+
${{ runner.os }}-toolchain-
139+
140+
- name: Cache Third Party Directory
141+
id: cache-thirdparty
142+
uses: actions/cache@v4
143+
with:
144+
path: third_party
145+
key: ${{ runner.os }}-thirdparty-v0.1
146+
restore-keys: |
147+
${{ runner.os }}-thirdparty-
148+
149+
- name: Download Build Artifact
150+
uses: actions/download-artifact@v4
151+
with:
152+
name: build-${{ matrix.xlen }}
153+
path: build${{ matrix.xlen }}
154+
155+
- name: Run tests
156+
run: |
157+
cd build${{ matrix.xlen }}
158+
source ci/toolchain_env.sh
159+
chmod -R +x . # Ensure all files have executable permissions
160+
if [ "${{ matrix.name }}" == "regression" ]; then
161+
./ci/regression.sh --unittest
162+
./ci/regression.sh --isa
163+
./ci/regression.sh --kernel
164+
./ci/regression.sh --regression
165+
else
166+
./ci/regression.sh --${{ matrix.name }}
167+
fi
168+
169+
vector-tests:
170+
runs-on: ubuntu-22.04
171+
needs: build
172+
strategy:
173+
fail-fast: false
174+
matrix:
175+
name: [vector]
121176
xlen: [32, 64]
122177

123178
steps:

‎ci/regression.sh.in‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -395,7 +395,7 @@ vector()
395395
echo "begin vector tests..."
396396

397397
make -C sim/simx clean && CONFIGS="-DEXT_V_ENABLE" make -C sim/simx
398-
TOOLDIR=@TOOLDIR@ XLEN=@XLEN@ VLEN=256 REG_TESTS=1 ./tests/riscv/riscv-vector-tests/run-test.sh
398+
TOOLDIR=@TOOLDIR@ XLEN=@XLEN@ VLEN=256 REG_TESTS=1 GEN_TESTS=0 ./tests/riscv/riscv-vector-tests/run-test.sh
399399

400400
echo "vector tests done!"
401401
}

‎hw/syn/xilinx/dut/common.mk‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -31,9 +31,9 @@ project_1/sources.txt:
3131
build: $(PROJECT).xpr
3232
$(PROJECT).xpr: project_1/sources.txt
3333
ifdef FPU_IP
34-
MAX_JOBS=$(JOBS) FPU_IP=project_1/ip SCRIPT_DIR=$(SCRIPT_DIR) $(VIVADO) -mode batch -source $(SRC_DIR)/project.tcl -tclargs $(TOP_LEVEL_ENTITY) $(DEVICE) project_1/sources.txt $(SRC_DIR)/project.xdc
34+
MAX_JOBS=$(JOBS) FPU_IP=project_1/ip TOOL_DIR=$(SCRIPT_DIR) $(VIVADO) -mode batch -source $(SRC_DIR)/project.tcl -tclargs $(TOP_LEVEL_ENTITY) $(DEVICE) project_1/sources.txt $(SRC_DIR)/project.xdc
3535
else
36-
MAX_JOBS=$(JOBS) SCRIPT_DIR=$(SCRIPT_DIR) $(VIVADO) -mode batch -source $(SRC_DIR)/project.tcl -tclargs $(TOP_LEVEL_ENTITY) $(DEVICE) project_1/sources.txt $(SRC_DIR)/project.xdc
36+
MAX_JOBS=$(JOBS) TOOL_DIR=$(SCRIPT_DIR) $(VIVADO) -mode batch -source $(SRC_DIR)/project.tcl -tclargs $(TOP_LEVEL_ENTITY) $(DEVICE) project_1/sources.txt $(SRC_DIR)/project.xdc
3737
endif
3838

3939
clean:

‎hw/syn/xilinx/dut/pre_opt_hook.tcl‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,2 @@
1+
set tool_dir $::env(TOOL_DIR)
2+
source ${tool_dir}/xilinx_async_bram_patch.tcl

‎hw/syn/xilinx/dut/project.tcl‎

Lines changed: 22 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -25,15 +25,15 @@ set device_part [lindex $::argv 1]
2525
set vcs_file [lindex $::argv 2]
2626
set xdc_file [lindex $::argv 3]
2727

28-
set script_dir $::env(SCRIPT_DIR)
29-
set source_dir [file dirname [info script]]
28+
set tool_dir $::env(TOOL_DIR)
29+
set script_dir [ file dirname [ file normalize [ info script ] ] ]
3030

3131
puts "Using top_module=$top_module"
3232
puts "Using device_part=$device_part"
3333
puts "Using vcs_file=$vcs_file"
3434
puts "Using xdc_file=$xdc_file"
35+
puts "Using tool_dir=$tool_dir"
3536
puts "Using script_dir=$script_dir"
36-
puts "Using source_dir=$source_dir"
3737

3838
# Set the number of jobs based on MAX_JOBS environment variable
3939
if {[info exists ::env(MAX_JOBS)]} {
@@ -46,7 +46,7 @@ if {[info exists ::env(MAX_JOBS)]} {
4646
proc run_setup {} {
4747
global project_name
4848
global top_module device_part vcs_file xdc_file
49-
global script_dir source_dir
49+
global script_dir tool_dir
5050
global num_jobs
5151
global argv argc ;# Using global system variables: argv and argc
5252

@@ -55,10 +55,10 @@ proc run_setup {} {
5555
set ip_dir $::env(FPU_IP)
5656
set argv [list $ip_dir $device_part]
5757
set argc 2
58-
source ${script_dir}/xilinx_ip_gen.tcl
58+
source ${tool_dir}/xilinx_ip_gen.tcl
5959
}
6060

61-
source "${script_dir}/parse_vcs_list.tcl"
61+
source "${tool_dir}/parse_vcs_list.tcl"
6262
set vlist [parse_vcs_list "${vcs_file}"]
6363

6464
set vsources_list [lindex $vlist 0]
@@ -96,12 +96,22 @@ proc run_setup {} {
9696
-objects [get_runs synth_1]
9797

9898
# register compilation hooks
99-
#set_property STEPS.SYNTH_DESIGN.TCL.PRE ${source_dir}/pre_synth_hook.tcl [get_runs synth_1]
100-
#set_property STEPS.SYNTH_DESIGN.TCL.POST ${source_dir}/post_synth_hook.tcl [get_runs synth_1]
101-
set_property STEPS.OPT_DESIGN.TCL.PRE ${script_dir}/xilinx_async_bram_patch.tcl [get_runs impl_1]
102-
#set_property STEPS.OPT_DESIGN.TCL.POST ${source_dir}/post_opt_hook.tcl [get_runs impl_1]
103-
#set_property STEPS.ROUTE_DESIGN.TCL.PRE ${source_dir}/pre_route_hook.tcl [get_runs impl_1]
104-
#set_property STEPS.ROUTE_DESIGN.TCL.POST ${source_dir}/post_route_hook.tcl [get_runs impl_1]
99+
#set_property STEPS.SYNTH_DESIGN.TCL.PRE ${script_dir}/pre_synth_hook.tcl [get_runs synth_1]
100+
#set_property STEPS.SYNTH_DESIGN.TCL.POST ${script_dir}/post_synth_hook.tcl [get_runs synth_1]
101+
set_property STEPS.OPT_DESIGN.TCL.PRE ${script_dir}/pre_opt_hook.tcl [get_runs impl_1]
102+
#set_property STEPS.OPT_DESIGN.TCL.POST ${script_dir}/post_opt_hook.tcl [get_runs impl_1]
103+
#set_property STEPS.POWER_OPT_DESIGN.TCL.PRE ${script_dir}/pre_power_opt_hook.tcl [get_runs impl_1]
104+
#set_property STEPS.POWER_OPT_DESIGN.TCL.POST ${script_dir}/post_power_opt_hook.tcl [get_runs impl_1]
105+
#set_property STEPS.PLACE_DESIGN.TCL.PRE ${script_dir}/pre_place_hook.tcl [get_runs impl_1]
106+
#set_property STEPS.PLACE_DESIGN.TCL.POST ${script_dir}/post_place_hook.tcl [get_runs impl_1]
107+
#set_property STEPS.POST_PLACE_POWER_OPT_DESIGN.TCL.PRE ${script_dir}/pre_place_power_opt_hook.tcl [get_runs impl_1]
108+
#set_property STEPS.POST_PLACE_POWER_OPT_DESIGN.TCL.POST ${script_dir}/post_place_power_opt_hook.tcl [get_runs impl_1]
109+
#set_property STEPS.PHYS_OPT_DESIGN.TCL.PRE ${script_dir}/pre_phys_opt_hook.tcl [get_runs impl_1]
110+
#set_property STEPS.PHYS_OPT_DESIGN.TCL.POST ${script_dir}/post_phys_opt_hook.tcl [get_runs impl_1]
111+
#set_property STEPS.ROUTE_DESIGN.TCL.PRE ${script_dir}/pre_route_hook.tcl [get_runs impl_1]
112+
#set_property STEPS.ROUTE_DESIGN.TCL.POST ${script_dir}/post_route_hook.tcl [get_runs impl_1]
113+
#set_property STEPS.WRITE_BITSTREAM.TCL.PRE ${script_dir}/pre_bitstream_hook.tcl [get_runs impl_1]
114+
#set_property STEPS.WRITE_BITSTREAM.TCL.POST ${script_dir}/post_bitstream_hook.tcl [get_runs impl_1]
105115

106116
update_compile_order -fileset sources_1
107117
}

‎hw/syn/xilinx/sandbox/Makefile‎

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -50,17 +50,26 @@ $(KERNEL).bin:
5050
kernel.bin.coe: $(KERNEL).bin
5151
$(SCRIPT_DIR)/bin2coe.py --out=$@ --binfile=8192:$(KERNEL).bin --depth=16384 --wordsize=64 --little_endian
5252

53+
pre_opt_hook.tcl: $(SRC_DIR)/pre_opt_hook.tcl
54+
cp $< $@
55+
56+
simulate.tcl: $(SRC_DIR)/simulate.tcl
57+
cp $< $@
58+
5359
gen-sources: project_1/sources.txt
5460
project_1/sources.txt:
5561
mkdir -p project_1
5662
$(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) -P -Cproject_1/src -Oproject_1/sources.txt
5763

5864
build: done.dcp
59-
done.dcp: project_1/sources.txt kernel.bin.coe project.tcl
60-
MAX_JOBS=$(JOBS) $(VIVADO) -mode batch -source project.tcl -tclargs $(DEVICE) project_1/sources.txt $(SCRIPT_DIR)
65+
done.dcp: project_1/sources.txt kernel.bin.coe project.tcl pre_opt_hook.tcl
66+
MAX_JOBS=$(JOBS) TOOL_DIR=$(SCRIPT_DIR) $(VIVADO) -mode batch -source project.tcl -tclargs $(DEVICE) project_1/sources.txt
6167
echo done > done.dcp
6268

63-
run: project_1/project_1.xpr
69+
run: simulate.tcl done.dcp
70+
MAX_JOBS=$(JOBS) TOOL_DIR=$(SCRIPT_DIR) $(VIVADO) -mode batch -source simulate.tcl -tclargs project_1/project_1.xpr 50000ns
71+
72+
open: done.dcp
6473
$(VIVADO) project_1/project_1.xpr &
6574

6675
clean:

‎hw/syn/xilinx/sandbox/pre_opt_hook.tcl‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,2 @@
1+
set tool_dir $::env(TOOL_DIR)
2+
source ${tool_dir}/xilinx_async_bram_patch.tcl

‎hw/syn/xilinx/sandbox/project.tcl.in‎

Lines changed: 27 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -11,19 +11,22 @@
1111
# See the License for the specific language governing permissions and
1212
# limitations under the License.
1313

14-
if { $::argc != 3 } {
15-
puts "ERROR: Program \"$::argv0\" requires 3 arguments!\n"
16-
puts "Usage: $::argv0 <device_part> <vcs_file> <tool_dir>\n"
14+
if { $::argc != 2 } {
15+
puts "ERROR: Program \"$::argv0\" requires 2 arguments!\n"
16+
puts "Usage: $::argv0 <device_part> <vcs_file>\n"
1717
exit
1818
}
1919

2020
set device_part [lindex $::argv 0]
2121
set vcs_file [lindex $::argv 1]
22-
set tool_dir [lindex $::argv 2]
22+
23+
set tool_dir $::env(TOOL_DIR)
24+
set script_dir [ file dirname [ file normalize [ info script ] ] ]
2325

2426
puts "Using device_part=$device_part"
2527
puts "Using vcs_file=$vcs_file"
2628
puts "Using tool_dir=$tool_dir"
29+
puts "Using script_dir=$script_dir"
2730

2831
# Set the number of jobs based on MAX_JOBS environment variable
2932
if {[info exists ::env(MAX_JOBS)]} {
@@ -35,7 +38,8 @@ if {[info exists ::env(MAX_JOBS)]} {
3538
}
3639

3740
proc run_setup {} {
38-
global device_part vcs_file tool_dir
41+
global device_part vcs_file
42+
global tool_dir script_dir
3943

4044
# Set the project name
4145
set project_name "project_1"
@@ -399,6 +403,24 @@ proc run_setup {} {
399403
set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse design_1.bd] -top]
400404
add_files -norecurse -fileset sources_1 $wrapper_path
401405

406+
# register compilation hooks
407+
#set_property STEPS.SYNTH_DESIGN.TCL.PRE ${script_dir}/pre_synth_hook.tcl [get_runs synth_1]
408+
#set_property STEPS.SYNTH_DESIGN.TCL.POST ${script_dir}/post_synth_hook.tcl [get_runs synth_1]
409+
set_property STEPS.OPT_DESIGN.TCL.PRE ${script_dir}/pre_opt_hook.tcl [get_runs impl_1]
410+
#set_property STEPS.OPT_DESIGN.TCL.POST ${script_dir}/post_opt_hook.tcl [get_runs impl_1]
411+
#set_property STEPS.POWER_OPT_DESIGN.TCL.PRE ${script_dir}/pre_power_opt_hook.tcl [get_runs impl_1]
412+
#set_property STEPS.POWER_OPT_DESIGN.TCL.POST ${script_dir}/post_power_opt_hook.tcl [get_runs impl_1]
413+
#set_property STEPS.PLACE_DESIGN.TCL.PRE ${script_dir}/pre_place_hook.tcl [get_runs impl_1]
414+
#set_property STEPS.PLACE_DESIGN.TCL.POST ${script_dir}/post_place_hook.tcl [get_runs impl_1]
415+
#set_property STEPS.POST_PLACE_POWER_OPT_DESIGN.TCL.PRE ${script_dir}/pre_place_power_opt_hook.tcl [get_runs impl_1]
416+
#set_property STEPS.POST_PLACE_POWER_OPT_DESIGN.TCL.POST ${script_dir}/post_place_power_opt_hook.tcl [get_runs impl_1]
417+
#set_property STEPS.PHYS_OPT_DESIGN.TCL.PRE ${script_dir}/pre_phys_opt_hook.tcl [get_runs impl_1]
418+
#set_property STEPS.PHYS_OPT_DESIGN.TCL.POST ${script_dir}/post_phys_opt_hook.tcl [get_runs impl_1]
419+
#set_property STEPS.ROUTE_DESIGN.TCL.PRE ${script_dir}/pre_route_hook.tcl [get_runs impl_1]
420+
#set_property STEPS.ROUTE_DESIGN.TCL.POST ${script_dir}/post_route_hook.tcl [get_runs impl_1]
421+
#set_property STEPS.WRITE_BITSTREAM.TCL.PRE ${script_dir}/pre_bitstream_hook.tcl [get_runs impl_1]
422+
#set_property STEPS.WRITE_BITSTREAM.TCL.POST ${script_dir}/post_bitstream_hook.tcl [get_runs impl_1]
423+
402424
update_compile_order -fileset sources_1
403425
}
404426

@@ -419,8 +441,6 @@ proc run_synthesis {} {
419441

420442
proc run_implementation {} {
421443
global tool_dir num_jobs
422-
source "${tool_dir}/ila_insert.tcl"
423-
insert_ila 8192
424444

425445
# Implementation
426446
if {$num_jobs != 0} {

‎hw/syn/xilinx/sandbox/simulate.tcl‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
# Copyright © 2019-2023
2+
#
3+
# Licensed under the Apache License, Version 2.0 (the "License");
4+
# you may not use this file except in compliance with the License.
5+
# You may obtain a copy of the License at
6+
# http://www.apache.org/licenses/LICENSE-2.0
7+
#
8+
# Unless required by applicable law or agreed to in writing, software
9+
# distributed under the License is distributed on an "AS IS" BASIS,
10+
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
11+
# See the License for the specific language governing permissions and
12+
# limitations under the License.
13+
14+
if { $::argc != 2 } {
15+
puts "ERROR: Program \"$::argv0\" requires 2 arguments!\n"
16+
puts "Usage: $::argv0 <project> <simtime>\n"
17+
exit
18+
}
19+
20+
set project_file [lindex $::argv 0]
21+
set sim_time [lindex $::argv 1]
22+
23+
set tb_name testbench ;# Replace with actual testbench module
24+
25+
open_project $project_file ;# Ensure correct project is loaded
26+
27+
# Ensure testbench is set as simulation top
28+
set_property top $tb_name [get_filesets sim_1]
29+
30+
# Launch the simulation
31+
launch_simulation -mode behavioral
32+
33+
# Run for the specified number of cycles
34+
run $sim_time

‎hw/syn/xilinx/xrt/Makefile‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -90,7 +90,7 @@ VPP_FLAGS += --link --target $(TARGET) --platform $(PLATFORM) --save-temps --no_
9090
VPP_FLAGS += --vivado.synth.jobs $(JOBS) --vivado.impl.jobs $(JOBS)
9191

9292
# register compilation hooks
93-
VPP_FLAGS += --xp "vivado_prop:run.impl_1.STEPS.OPT_DESIGN.TCL.PRE={$(SCRIPT_DIR)/xilinx_async_bram_patch.tcl}"
93+
VPP_FLAGS += --xp "vivado_prop:run.impl_1.STEPS.OPT_DESIGN.TCL.PRE=${SRC_DIR}/pre_opt_hook.tcl"
9494

9595
# load platform settings
9696
include $(SRC_DIR)/platforms.mk
@@ -166,11 +166,11 @@ $(BIN_DIR)/scope.json: $(BUILD_DIR)/vortex.xml
166166

167167
gen-xo: $(XO_CONTAINER)
168168
$(XO_CONTAINER): $(BUILD_DIR)/sources.txt
169-
mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(VIVADO) -mode batch -source $(SRC_DIR)/gen_xo.tcl -tclargs ../$(XO_CONTAINER) vortex_afu sources.txt $(SCRIPT_DIR) ../$(BUILD_DIR)
169+
mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); TOOL_DIR=$(SCRIPT_DIR) $(VIVADO) -mode batch -source $(SRC_DIR)/gen_xo.tcl -tclargs ../$(XO_CONTAINER) vortex_afu sources.txt ../$(BUILD_DIR)
170170

171171
gen-bin: $(XCLBIN_CONTAINER)
172172
$(XCLBIN_CONTAINER): $(XO_CONTAINER) $(SCOPE_JSON)
173-
mkdir -p $(BIN_DIR); cd $(BUILD_DIR); $(VPP) $(VPP_FLAGS) -o ../$(XCLBIN_CONTAINER) ../$(XO_CONTAINER)
173+
mkdir -p $(BIN_DIR); cd $(BUILD_DIR); TOOL_DIR=$(SCRIPT_DIR) $(VPP) $(VPP_FLAGS) -o ../$(XCLBIN_CONTAINER) ../$(XO_CONTAINER)
174174

175175
emconfig: $(BIN_DIR)/emconfig.json
176176
$(BIN_DIR)/emconfig.json:
@@ -183,6 +183,7 @@ ifeq ($(TARGET), hw)
183183
cp $(BUILD_DIR)/_x/reports/link/syn/ulp_vortex_afu_1_0_synth_1_ulp_vortex_afu_1_0_utilization_synth.rpt $(BUILD_DIR)/bin
184184
cp $(BUILD_DIR)/_x/reports/link/imp/impl_1_hw_bb_locked_utilization_placed.rpt $(BUILD_DIR)/bin
185185
cp $(BUILD_DIR)/_x/reports/link/imp/impl_1_hw_bb_locked_timing_summary_routed.rpt $(BUILD_DIR)/bin
186+
cp $(BUILD_DIR)/_x/link/vivado/vpl/prj/prj.runs/impl_1/hier_utilization.rpt $(BUILD_DIR)/bin
186187
endif
187188

188189
chipscope:

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