From 20683e70e41f574b52b90334401ed499c40b11db Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 17 Oct 2024 16:50:59 +0200 Subject: [PATCH 1/3] synth: clockgate command demo for sky130hd Signed-off-by: Emil J. Tywoniak --- flow/platforms/sky130hd/config.mk | 3 +++ flow/scripts/synth.tcl | 2 ++ 2 files changed, 5 insertions(+) diff --git a/flow/platforms/sky130hd/config.mk b/flow/platforms/sky130hd/config.mk index 165cf2f3dc..ac2b5b0721 100644 --- a/flow/platforms/sky130hd/config.mk +++ b/flow/platforms/sky130hd/config.mk @@ -77,6 +77,9 @@ export ADDER_MAP_FILE ?= $(PLATFORM_DIR)/cells_adders_hd.v # Define ABC driver and load export ABC_DRIVER_CELL = sky130_fd_sc_hd__buf_1 export ABC_LOAD_IN_FF = 5 + +export CLOCKGATE_CMD = clockgate -pos sky130_fd_sc_hd__dlclkp_4 GATE:CLK:GCLK -min_net_size 8 + #-------------------------------------------------------- # Floorplan # ------------------------------------------------------- diff --git a/flow/scripts/synth.tcl b/flow/scripts/synth.tcl index ec1c3445c8..46857b3bd2 100644 --- a/flow/scripts/synth.tcl +++ b/flow/scripts/synth.tcl @@ -40,6 +40,8 @@ foreach cell $::env(DONT_USE_CELLS) { lappend dfflibmap_args -dont_use $cell } +yosys $::env(CLOCKGATE_CMD) + # Technology mapping of flip-flops # dfflibmap only supports one liberty file if {[env_var_exists_and_non_empty DFF_LIB_FILE]} { From 54dd5220b76e35858c9c2c550cb709935b7a627a Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Fri, 18 Oct 2024 10:24:30 +0200 Subject: [PATCH 2/3] clockgate for more PDKs --- flow/platforms/asap7/config.mk | 3 +++ flow/platforms/ihp-sg13g2/config.mk | 3 +++ flow/platforms/nangate45/config.mk | 2 ++ flow/platforms/sky130hs/config.mk | 2 ++ 4 files changed, 10 insertions(+) diff --git a/flow/platforms/asap7/config.mk b/flow/platforms/asap7/config.mk index 3e4d965336..377ca9bee0 100644 --- a/flow/platforms/asap7/config.mk +++ b/flow/platforms/asap7/config.mk @@ -80,6 +80,7 @@ export DONT_USE_CELLS += SDF* ICG* # Yosys mapping files export LATCH_MAP_FILE = $(PLATFORM_DIR)/yoSys/cells_latch_R.v export CLKGATE_MAP_FILE = $(PLATFORM_DIR)/yoSys/cells_clkgate_R.v +export CLOCKGATE_CMD = clockgate -pos ICGx1_ASAP7_75t_R ENA:CLK:GCLK -min_net_size 8 -tie_lo SE export ADDER_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_adders_R.v export MAX_UNGROUP_SIZE ?= 100 @@ -176,6 +177,7 @@ ifeq ($(ASAP7_USELVT), 1) export LATCH_MAP_FILE = $(PLATFORM_DIR)/yoSys/cells_latch_L.v export CLKGATE_MAP_FILE = $(PLATFORM_DIR)/yoSys/cells_clkgate_L.v + export CLOCKGATE_CMD = clockgate -pos ICGx1_ASAP7_75t_L ENA:CLK:GCLK -min_net_size 8 -tie_lo SE export ADDER_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_adders_L.v export BC_NLDM_DFF_LIB_FILE = $(LIB_DIR)/asap7sc7p5t_SEQ_LVT_FF_nldm_220123.lib @@ -225,6 +227,7 @@ ifeq ($(ASAP7_USESLVT), 1) export LATCH_MAP_FILE = $(PLATFORM_DIR)/yoSys/cells_latch_SL.v export CLKGATE_MAP_FILE = $(PLATFORM_DIR)/yoSys/cells_clkgate_SL.v + export CLOCKGATE_CMD = clockgate -pos ICGx1_ASAP7_75t_SL ENA:CLK:GCLK -min_net_size 8 -tie_lo SE export ADDER_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_adders_SL.v export BC_NLDM_DFF_LIB_FILE = $(LIB_DIR)/asap7sc7p5t_SEQ_SLVT_FF_nldm_220123.lib diff --git a/flow/platforms/ihp-sg13g2/config.mk b/flow/platforms/ihp-sg13g2/config.mk index 176cd3831f..04f71ca3a6 100644 --- a/flow/platforms/ihp-sg13g2/config.mk +++ b/flow/platforms/ihp-sg13g2/config.mk @@ -56,6 +56,9 @@ export ABC_DRIVER_CELL = sg13g2_buf_4 export ABC_LOAD_IN_FF = 6.0 # Set yosys-abc clock period to first "clk_period" value or "-period" value found in sdc file export ABC_CLOCK_PERIOD_IN_PS ?= $(shell sed -nE "s/^set clk_period (.+)|.* -period (.+) .*/\1\2/p" $(SDC_FILE) | head -1 | awk '{print $$1*1000}') + +export CLOCKGATE_CMD = clockgate -pos sg13g2_lgcp_1 GATE:CLK:GCLK -min_net_size 8 + #-------------------------------------------------------- # Floorplan # ------------------------------------------------------- diff --git a/flow/platforms/nangate45/config.mk b/flow/platforms/nangate45/config.mk index 919217f716..a972c03c5e 100644 --- a/flow/platforms/nangate45/config.mk +++ b/flow/platforms/nangate45/config.mk @@ -41,6 +41,8 @@ export ABC_DRIVER_CELL = BUF_X1 # BUF_X1, pin (A) = 0.974659. Arbitrarily multiply by 4 export ABC_LOAD_IN_FF = 3.898 +export CLOCKGATE_CMD = clockgate -pos CLKGATE_X1 E:CK:GCK -min_net_size 8 + #-------------------------------------------------------- # Floorplan # ------------------------------------------------------- diff --git a/flow/platforms/sky130hs/config.mk b/flow/platforms/sky130hs/config.mk index 69fbd842d6..956ce61fe4 100644 --- a/flow/platforms/sky130hs/config.mk +++ b/flow/platforms/sky130hs/config.mk @@ -39,6 +39,8 @@ export ADDER_MAP_FILE ?= $(PLATFORM_DIR)/cells_adders_hs.v # Define ABC driver and load export ABC_DRIVER_CELL = sky130_fd_sc_hs__buf_1 export ABC_LOAD_IN_FF = 5 +export CLOCKGATE_CMD = clockgate -pos sky130_fd_sc_hs__dlclkp_4 GATE:CLK:GCLK -min_net_size 8 + #-------------------------------------------------------- # Floorplan # ------------------------------------------------------- From 245949202742ee7cb85788686a1512d188ef1008 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Fri, 18 Oct 2024 10:25:21 +0200 Subject: [PATCH 3/3] make sure synth runs even if no clockgate command --- flow/scripts/synth.tcl | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/flow/scripts/synth.tcl b/flow/scripts/synth.tcl index 46857b3bd2..eeb5689609 100644 --- a/flow/scripts/synth.tcl +++ b/flow/scripts/synth.tcl @@ -40,7 +40,9 @@ foreach cell $::env(DONT_USE_CELLS) { lappend dfflibmap_args -dont_use $cell } -yosys $::env(CLOCKGATE_CMD) +if {[env_var_exists_and_non_empty CLOCKGATE_CMD]} { + yosys $::env(CLOCKGATE_CMD) +} # Technology mapping of flip-flops # dfflibmap only supports one liberty file