From e148056c8e2eca4d7844a3b2f3b1bf0c27b078b8 Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Wed, 17 Dec 2025 16:43:46 +0000 Subject: [PATCH] Reapply "Merge pull request #8949 from luis201420/cts_improve_automatic_clustering" This reverts commit fb385c1a1a1759d2e5a3166a40cd0d9ace6e0bc9. Signed-off-by: Eder Monteiro --- src/cts/src/CtsOptions.cpp | 9 +- src/cts/src/CtsOptions.h | 24 +-- src/cts/src/HTreeBuilder.cpp | 96 ++++------ src/cts/src/SinkClustering.cpp | 24 ++- src/cts/src/SinkClustering.h | 2 + src/cts/test/array.ok | 83 ++++----- src/cts/test/array_ins_delay.ok | 73 ++++---- src/cts/test/array_no_blockages.ok | 73 ++++---- src/cts/test/array_repair_clock_nets.ok | 196 ++++++++++----------- src/cts/test/check_max_fanout3.ok | 5 +- src/cts/test/gated_clock1.ok | 2 +- src/cts/test/inverters.ok | 2 +- src/cts/test/skip_nets.ok | 2 +- test/aes_nangate45.metrics | 74 ++++---- test/aes_nangate45.metrics_limits | 22 +-- test/jpeg_sky130hd.metrics | 174 +++++++++--------- test/jpeg_sky130hd.metrics_limits | 26 +-- test/jpeg_sky130hs.metrics | 215 +++++++++++------------ test/jpeg_sky130hs.metrics_limits | 24 +-- test/tinyRocket_nangate45.metrics | 64 ++++--- test/tinyRocket_nangate45.metrics_limits | 20 +-- 21 files changed, 579 insertions(+), 631 deletions(-) diff --git a/src/cts/src/CtsOptions.cpp b/src/cts/src/CtsOptions.cpp index 438b19c50f1..922329aa8e7 100644 --- a/src/cts/src/CtsOptions.cpp +++ b/src/cts/src/CtsOptions.cpp @@ -31,14 +31,11 @@ void CtsOptions::inDbInstCreate(odb::dbInst* inst, odb::dbRegion* region) void CtsOptions::limitSinkClusteringSizes(unsigned limit) { + unsigned new_size = limit; if (sinkClustersSizeSet_) { - setSinkClusteringSize(std::min(limit, sinkClustersSize_)); - return; + new_size = std::min(new_size, sinkClustersSize_); } - auto lowerBound = std::lower_bound( - sinkClusteringSizes_.begin(), sinkClusteringSizes_.end(), limit); - sinkClusteringSizes_.erase(lowerBound, sinkClusteringSizes_.end()); - sinkClusteringSizes_.push_back(limit); + setSinkClusteringSize(new_size); } void CtsOptions::recordBuffer(odb::dbMaster* master, MasterType type) diff --git a/src/cts/src/CtsOptions.h b/src/cts/src/CtsOptions.h index 532be7f49dc..7dc29631b0b 100644 --- a/src/cts/src/CtsOptions.h +++ b/src/cts/src/CtsOptions.h @@ -84,11 +84,6 @@ class CtsOptions : public odb::dbBlockCallBackObj void setSinkClustering(bool enable) { sinkClusteringEnable_ = enable; } bool getSinkClustering() const { return sinkClusteringEnable_; } - void setSinkClusteringUseMaxCap(bool useMaxCap) - { - sinkClusteringUseMaxCap_ = useMaxCap; - } - bool getSinkClusteringUseMaxCap() const { return sinkClusteringUseMaxCap_; } void setNumMaxLeafSinks(unsigned numSinks) { numMaxLeafSinks_ = numSinks; } unsigned getNumMaxLeafSinks() const { return numMaxLeafSinks_; } void setMaxSlew(unsigned slew) { maxSlew_ = slew; } @@ -209,38 +204,26 @@ class CtsOptions : public odb::dbBlockCallBackObj void setMaxDiameter(double distance) { maxDiameter_ = distance; - sinkClusteringUseMaxCap_ = false; maxDiameterSet_ = true; } void resetMaxDiameter() { maxDiameter_ = 50; - sinkClusteringUseMaxCap_ = true; maxDiameterSet_ = false; } bool isMaxDiameterSet() const { return maxDiameterSet_; } - const std::vector& getSinkClusteringDiameters() - { - return sinkClusteringDiameters_; - } unsigned getSinkClusteringSize() const { return sinkClustersSize_; } void setSinkClusteringSize(unsigned size) { sinkClustersSize_ = size; - sinkClusteringUseMaxCap_ = false; sinkClustersSizeSet_ = true; } void resetSinkClusteringSize() { - sinkClustersSize_ = 20; - sinkClusteringUseMaxCap_ = true; + sinkClustersSize_ = 30; sinkClustersSizeSet_ = false; } bool isSinkClusteringSizeSet() const { return sinkClustersSizeSet_; } - const std::vector& getSinkClusteringSizes() - { - return sinkClusteringSizes_; - } void limitSinkClusteringSizes(unsigned limit); unsigned getSinkClusteringLevels() const { return sinkClusteringLevels_; } void setSinkClusteringLevels(unsigned levels) @@ -363,7 +346,6 @@ class CtsOptions : public odb::dbBlockCallBackObj unsigned wireSegmentUnit_ = 0; bool plotSolution_ = false; bool sinkClusteringEnable_ = true; - bool sinkClusteringUseMaxCap_ = true; bool simpleSegmentsEnable_ = false; bool vertexBuffersEnable_ = false; std::unique_ptr observer_; @@ -390,10 +372,8 @@ class CtsOptions : public odb::dbBlockCallBackObj int sinks_ = 0; double maxDiameter_ = 50; bool maxDiameterSet_ = false; - std::vector sinkClusteringDiameters_ = {50, 100, 200}; - unsigned sinkClustersSize_ = 20; + unsigned sinkClustersSize_ = 30; bool sinkClustersSizeSet_ = false; - std::vector sinkClusteringSizes_ = {10, 20, 30}; double macroMaxDiameter_ = 50; bool macroMaxDiameterSet_ = false; unsigned macroSinkClustersSize_ = 4; diff --git a/src/cts/src/HTreeBuilder.cpp b/src/cts/src/HTreeBuilder.cpp index 5e0eb02ec2c..985977fd976 100644 --- a/src/cts/src/HTreeBuilder.cpp +++ b/src/cts/src/HTreeBuilder.cpp @@ -81,63 +81,15 @@ void HTreeBuilder::preSinkClustering( unsigned bestClusterSize = 0; float bestDiameter = 0.0; - if (clusterSizeSet && maxDiameterSet) { - // clang-format off - debugPrint(logger_, CTS, "clustering", 1, "**** match.run({}, {}, {}) ****", - clusterSize, maxDiameter, wireSegmentUnit_); - // clang-format on - matching.run(clusterSize, - maxDiameter, - wireSegmentUnit_, - bestClusterSize, - bestDiameter); - } else if (!clusterSizeSet && maxDiameterSet) { - // only diameter is set, try clustering sizes of 10, 20 and 30 - for (unsigned clusterSize2 : options_->getSinkClusteringSizes()) { - // clang-format off - debugPrint(logger_, CTS, "clustering", 1, "**** match.run({}, {}, {}) ****", - clusterSize2, maxDiameter, wireSegmentUnit_); - // clang-format on - matching.run(clusterSize2, - maxDiameter, - wireSegmentUnit_, - bestClusterSize, - bestDiameter); - } - } else if (clusterSizeSet && !maxDiameterSet) { - // only clustering size is set, try diameters of 50, 100 and 200 um - for (unsigned clusterDiameter2 : options_->getSinkClusteringDiameters()) { - // clang-format off - debugPrint(logger_, CTS, "clustering", 1, "**** match.run({}, {}, {}) ****", - clusterSize, clusterDiameter2, wireSegmentUnit_); - // clang-format on - float maxDiameter2 = clusterDiameter2 * (float) options_->getDbUnits() - / wireSegmentUnit_; - matching.run(clusterSize, - maxDiameter2, - wireSegmentUnit_, - bestClusterSize, - bestDiameter); - } - } else { // neighther clustering size nor diameter is set - // try diameters of 50, 100 and 200 um - for (unsigned clusterDiameter2 : clusterDiameters()) { - // try clustering sizes of 10, 20 and 30 - for (unsigned clusterSize2 : options_->getSinkClusteringSizes()) { - // clang-format off - debugPrint(logger_, CTS, "clustering", 1, "**** match.run({}, {}, {}) ****", - clusterSize2, clusterDiameter2, wireSegmentUnit_); - // clang-format on - float maxDiameter2 = clusterDiameter2 * (float) options_->getDbUnits() - / wireSegmentUnit_; - matching.run(clusterSize2, - maxDiameter2, - wireSegmentUnit_, - bestClusterSize, - bestDiameter); - } - } - } + // clang-format off + debugPrint(logger_, CTS, "clustering", 1, "**** match.run({}, {}, {}) ****", + clusterSize, maxDiameter, wireSegmentUnit_); + // clang-format on + matching.run(clusterSize, + maxDiameter, + wireSegmentUnit_, + bestClusterSize, + bestDiameter); if (clusterSizeSet || maxDiameterSet) { logger_->info( @@ -1177,18 +1129,21 @@ void HTreeBuilder::run() unsigned clusterSize = (type_ == TreeType::MacroTree) ? options_->getMacroSinkClusteringSize() : options_->getSinkClusteringSize(); + bool use_max_diameter = (type_ == TreeType::MacroTree) + ? options_->isMacroMaxDiameterSet() + : options_->isMaxDiameterSet(); + bool use_max_size = (type_ == TreeType::MacroTree) + ? options_->isMacroSinkClusteringSizeSet() + : options_->isSinkClusteringSizeSet(); bool useMaxCap = (type_ == TreeType::MacroTree) ? false - : options_->getSinkClusteringUseMaxCap(); + : !(use_max_size && use_max_diameter); logger_->info( CTS, 27, "Generating H-Tree topology for net {}.", clock_.getName()); logger_->info(CTS, 28, " Total number of sinks: {}.", clock_.getNumSinks()); if (options_->getSinkClustering()) { - if (useMaxCap) { - logger_->info( - CTS, 90, " Sinks will be clustered based on buffer max cap."); - } else { + if (!useMaxCap) { logger_->info( CTS, 29, @@ -1197,6 +1152,23 @@ void HTreeBuilder::run() type_ == TreeType::MacroTree ? "Macro " : "Register", clusterSize, clusterDiameter); + } else if (use_max_diameter && !use_max_size) { + logger_->info(CTS, + 59, + " {} sinks will be clustered with maximum cluster diameter " + "of {:.1f} um and based on buffer max cap.", + type_ == TreeType::MacroTree ? "Macro " : "Register", + clusterDiameter); + } else if (!use_max_diameter && use_max_size) { + logger_->info(CTS, + 60, + " {} sinks will be clustered in groups of up to {} and " + "based on buffer max cap.", + type_ == TreeType::MacroTree ? "Macro " : "Register", + clusterSize); + } else { + logger_->info( + CTS, 90, " Sinks will be clustered based on buffer max cap."); } } logger_->info( diff --git a/src/cts/src/SinkClustering.cpp b/src/cts/src/SinkClustering.cpp index 66762660082..18dc95ef752 100644 --- a/src/cts/src/SinkClustering.cpp +++ b/src/cts/src/SinkClustering.cpp @@ -12,6 +12,7 @@ #include #include +#include "TreeBuilder.h" #include "Util.h" #include "stt/SteinerTreeBuilder.h" #include "utl/Logger.h" @@ -29,9 +30,15 @@ SinkClustering::SinkClustering(const CtsOptions* options, techChar_(techChar), maxInternalDiameter_(10), capPerUnit_(0.0), + use_max_diameter_((HTree->getTreeType() == TreeType::MacroTree) + ? options->isMacroMaxDiameterSet() + : options->isMaxDiameterSet()), + use_max_size_((HTree->getTreeType() == TreeType::MacroTree) + ? options->isMacroSinkClusteringSizeSet() + : options->isSinkClusteringSizeSet()), useMaxCapLimit_((HTree->getTreeType() == TreeType::MacroTree) ? false - : options->getSinkClusteringUseMaxCap()), + : !(use_max_size_ && use_max_diameter_)), scaleFactor_(1), HTree_(HTree) { @@ -415,11 +422,20 @@ bool SinkClustering::isLimitExceeded(const unsigned size, const double capCost, const unsigned sizeLimit) { + bool is_limit_exceeded = false; if (useMaxCapLimit_) { - return (capCost > options_->getSinkBufferInputCap() * max_cap__factor_); + is_limit_exceeded + |= (capCost > options_->getSinkBufferInputCap() * max_cap__factor_); } - - return (size >= sizeLimit || cost > maxInternalDiameter_); + // size is defined by the user + if (use_max_size_) { + is_limit_exceeded |= (size >= sizeLimit); + } + // diameter is defined by the user + if (use_max_diameter_) { + is_limit_exceeded |= (cost > maxInternalDiameter_); + } + return is_limit_exceeded; } void SinkClustering::writePlotFile(unsigned groupSize) diff --git a/src/cts/src/SinkClustering.h b/src/cts/src/SinkClustering.h index 009d3d63143..ace8372574f 100644 --- a/src/cts/src/SinkClustering.h +++ b/src/cts/src/SinkClustering.h @@ -90,6 +90,8 @@ class SinkClustering std::vector> bestSolution_; float maxInternalDiameter_; float capPerUnit_; + bool use_max_diameter_; + bool use_max_size_; bool useMaxCapLimit_; int scaleFactor_; static constexpr double max_cap__factor_ = 10; diff --git a/src/cts/test/array.ok b/src/cts/test/array.ok index fc9cab85438..547fce19fea 100644 --- a/src/cts/test/array.ok +++ b/src/cts/test/array.ok @@ -50,54 +50,49 @@ [INFO CTS-0201] 225 blockages from hard placement blockages and placed macros will be used. [INFO CTS-0027] Generating H-Tree topology for net clk_regs. [INFO CTS-0028] Total number of sinks: 2250. -[INFO CTS-0029] Register sinks will be clustered in groups of up to 20 and with maximum cluster diameter of 100.0 um. +[INFO CTS-0059] Register sinks will be clustered with maximum cluster diameter of 100.0 um and based on buffer max cap. [INFO CTS-0030] Number of static layers: 0. [INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). -[INFO CTS-0204] A clustering solution was found from clustering size of 10 and clustering diameter of 100. +[INFO CTS-0204] A clustering solution was found from clustering size of 30 and clustering diameter of 100. [INFO CTS-0205] Better solution may be possible if either -sink_clustering_size, -sink_clustering_max_diameter, or both options are omitted to enable automatic clustering. -[INFO CTS-0019] Total number of sinks after clustering: 227. -[INFO CTS-0024] Normalized sink region: [(189.626, 2.21643), (661.055, 670.416)]. +[INFO CTS-0019] Total number of sinks after clustering: 136. +[INFO CTS-0024] Normalized sink region: [(189.626, 2.41643), (661.055, 670.416)]. [INFO CTS-0025] Width: 471.4286. -[INFO CTS-0026] Height: 668.2000. +[INFO CTS-0026] Height: 668.0000. Level 1 Direction: Vertical - Sinks per sub-region: 114 - Sub-region size: 471.4286 X 334.1000 -[INFO CTS-0034] Segment length (rounded): 168. + Sinks per sub-region: 68 + Sub-region size: 471.4286 X 334.0000 +[INFO CTS-0034] Segment length (rounded): 166. Level 2 Direction: Horizontal - Sinks per sub-region: 57 - Sub-region size: 235.7143 X 334.1000 + Sinks per sub-region: 34 + Sub-region size: 235.7143 X 334.0000 [INFO CTS-0034] Segment length (rounded): 118. Level 3 Direction: Vertical - Sinks per sub-region: 29 - Sub-region size: 235.7143 X 167.0500 + Sinks per sub-region: 17 + Sub-region size: 235.7143 X 167.0000 [INFO CTS-0034] Segment length (rounded): 84. Level 4 Direction: Horizontal - Sinks per sub-region: 15 - Sub-region size: 117.8572 X 167.0500 + Sinks per sub-region: 9 + Sub-region size: 117.8572 X 167.0000 [INFO CTS-0034] Segment length (rounded): 58. - Level 5 - Direction: Vertical - Sinks per sub-region: 8 - Sub-region size: 117.8572 X 83.5250 -[INFO CTS-0034] Segment length (rounded): 42. [INFO CTS-0032] Stop criterion found. Max number of sinks is 15. -[INFO CTS-0035] Number of sinks covered: 227. +[INFO CTS-0035] Number of sinks covered: 136. [INFO CTS-0018] Created 190 clock buffers. [INFO CTS-0012] Minimum number of buffers in the clock path: 16. [INFO CTS-0013] Maximum number of buffers in the clock path: 17. [INFO CTS-0015] Created 190 clock nets. [INFO CTS-0016] Fanout distribution for the current clock = 2:103, 6:1, 7:6, 8:7, 9:2.. [INFO CTS-0017] Max level of the clock tree: 4. -[INFO CTS-0018] Created 366 clock buffers. -[INFO CTS-0012] Minimum number of buffers in the clock path: 17. -[INFO CTS-0013] Maximum number of buffers in the clock path: 17. -[INFO CTS-0015] Created 366 clock nets. -[INFO CTS-0016] Fanout distribution for the current clock = 2:1, 4:3, 5:9, 6:5, 7:4, 8:3, 9:4, 10:230.. -[INFO CTS-0017] Max level of the clock tree: 5. +[INFO CTS-0018] Created 211 clock buffers. +[INFO CTS-0012] Minimum number of buffers in the clock path: 15. +[INFO CTS-0013] Maximum number of buffers in the clock path: 15. +[INFO CTS-0015] Created 211 clock nets. +[INFO CTS-0016] Fanout distribution for the current clock = 4:1, 5:2, 6:3, 7:2, 8:1, 9:5, 10:44, 11:1, 12:3, 20:90.. +[INFO CTS-0017] Max level of the clock tree: 4. [INFO CTS-0098] Clock net "clk" [INFO CTS-0099] Sinks 225 [INFO CTS-0100] Leaf buffers 103 @@ -105,35 +100,33 @@ [INFO CTS-0102] Path depth 16 - 17 [INFO CTS-0207] Dummy loads inserted 0 [INFO CTS-0098] Clock net "clk_regs" -[INFO CTS-0099] Sinks 2254 -[INFO CTS-0100] Leaf buffers 227 -[INFO CTS-0101] Average sink wire length 4121.94 um -[INFO CTS-0102] Path depth 17 - 17 -[INFO CTS-0207] Dummy loads inserted 4 +[INFO CTS-0099] Sinks 2296 +[INFO CTS-0100] Leaf buffers 136 +[INFO CTS-0101] Average sink wire length 3917.23 um +[INFO CTS-0102] Path depth 15 - 15 +[INFO CTS-0207] Dummy loads inserted 46 [INFO CTS-0033] Balancing latency for clock clk [INFO CTS-0036] inserted 3 delay buffers [INFO CTS-0037] Total number of delay buffers: 3 Total number of Clock Roots: 2. -Total number of Buffers Inserted: 556. -Total number of Clock Subnets: 556. +Total number of Buffers Inserted: 401. +Total number of Clock Subnets: 401. Total number of Sinks: 2475. Cells used: - BUF_X4: 560 + BUF_X4: 405 Dummys used: - BUF_X4: 2 - INV_X1: 1 - INV_X4: 1 + INV_X8: 46 [INFO RSZ-0058] Using max wire length 693um. -[INFO RSZ-0047] Found 41 long wires. -[INFO RSZ-0048] Inserted 165 buffers in 41 nets. +[INFO RSZ-0047] Found 35 long wires. +[INFO RSZ-0048] Inserted 204 buffers in 35 nets. Placement Analysis --------------------------------- -total displacement 4186.7 u -average displacement 1.3 u -max displacement 143.4 u -original HPWL 192698.4 u -legalized HPWL 193625.0 u -delta HPWL 0 % +total displacement 4400.8 u +average displacement 1.4 u +max displacement 137.7 u +original HPWL 182505.7 u +legalized HPWL 183634.8 u +delta HPWL 1 % Clock clk 1.03 source latency inst_5_4/clk ^ diff --git a/src/cts/test/array_ins_delay.ok b/src/cts/test/array_ins_delay.ok index d01a89cec1d..3652e6b2f0e 100644 --- a/src/cts/test/array_ins_delay.ok +++ b/src/cts/test/array_ins_delay.ok @@ -50,54 +50,49 @@ [INFO CTS-0201] 225 blockages from hard placement blockages and placed macros will be used. [INFO CTS-0027] Generating H-Tree topology for net clk_regs. [INFO CTS-0028] Total number of sinks: 2250. -[INFO CTS-0029] Register sinks will be clustered in groups of up to 20 and with maximum cluster diameter of 100.0 um. +[INFO CTS-0059] Register sinks will be clustered with maximum cluster diameter of 100.0 um and based on buffer max cap. [INFO CTS-0030] Number of static layers: 0. [INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). -[INFO CTS-0204] A clustering solution was found from clustering size of 10 and clustering diameter of 100. +[INFO CTS-0204] A clustering solution was found from clustering size of 30 and clustering diameter of 100. [INFO CTS-0205] Better solution may be possible if either -sink_clustering_size, -sink_clustering_max_diameter, or both options are omitted to enable automatic clustering. -[INFO CTS-0019] Total number of sinks after clustering: 227. -[INFO CTS-0024] Normalized sink region: [(189.626, 2.21643), (661.055, 670.416)]. +[INFO CTS-0019] Total number of sinks after clustering: 136. +[INFO CTS-0024] Normalized sink region: [(189.626, 2.41643), (661.055, 670.416)]. [INFO CTS-0025] Width: 471.4286. -[INFO CTS-0026] Height: 668.2000. +[INFO CTS-0026] Height: 668.0000. Level 1 Direction: Vertical - Sinks per sub-region: 114 - Sub-region size: 471.4286 X 334.1000 -[INFO CTS-0034] Segment length (rounded): 168. + Sinks per sub-region: 68 + Sub-region size: 471.4286 X 334.0000 +[INFO CTS-0034] Segment length (rounded): 166. Level 2 Direction: Horizontal - Sinks per sub-region: 57 - Sub-region size: 235.7143 X 334.1000 + Sinks per sub-region: 34 + Sub-region size: 235.7143 X 334.0000 [INFO CTS-0034] Segment length (rounded): 118. Level 3 Direction: Vertical - Sinks per sub-region: 29 - Sub-region size: 235.7143 X 167.0500 + Sinks per sub-region: 17 + Sub-region size: 235.7143 X 167.0000 [INFO CTS-0034] Segment length (rounded): 84. Level 4 Direction: Horizontal - Sinks per sub-region: 15 - Sub-region size: 117.8572 X 167.0500 + Sinks per sub-region: 9 + Sub-region size: 117.8572 X 167.0000 [INFO CTS-0034] Segment length (rounded): 58. - Level 5 - Direction: Vertical - Sinks per sub-region: 8 - Sub-region size: 117.8572 X 83.5250 -[INFO CTS-0034] Segment length (rounded): 42. [INFO CTS-0032] Stop criterion found. Max number of sinks is 15. -[INFO CTS-0035] Number of sinks covered: 227. +[INFO CTS-0035] Number of sinks covered: 136. [INFO CTS-0018] Created 190 clock buffers. [INFO CTS-0012] Minimum number of buffers in the clock path: 16. [INFO CTS-0013] Maximum number of buffers in the clock path: 17. [INFO CTS-0015] Created 190 clock nets. [INFO CTS-0016] Fanout distribution for the current clock = 2:103, 6:1, 7:6, 8:7, 9:2.. [INFO CTS-0017] Max level of the clock tree: 4. -[INFO CTS-0018] Created 366 clock buffers. -[INFO CTS-0012] Minimum number of buffers in the clock path: 17. -[INFO CTS-0013] Maximum number of buffers in the clock path: 17. -[INFO CTS-0015] Created 366 clock nets. -[INFO CTS-0016] Fanout distribution for the current clock = 2:1, 4:3, 5:9, 6:5, 7:4, 8:3, 9:4, 10:230.. -[INFO CTS-0017] Max level of the clock tree: 5. +[INFO CTS-0018] Created 211 clock buffers. +[INFO CTS-0012] Minimum number of buffers in the clock path: 15. +[INFO CTS-0013] Maximum number of buffers in the clock path: 15. +[INFO CTS-0015] Created 211 clock nets. +[INFO CTS-0016] Fanout distribution for the current clock = 4:1, 5:2, 6:3, 7:2, 8:1, 9:5, 10:44, 11:1, 12:3, 20:90.. +[INFO CTS-0017] Max level of the clock tree: 4. [INFO CTS-0098] Clock net "clk" [INFO CTS-0099] Sinks 225 [INFO CTS-0100] Leaf buffers 103 @@ -105,25 +100,25 @@ [INFO CTS-0102] Path depth 16 - 17 [INFO CTS-0207] Dummy loads inserted 0 [INFO CTS-0098] Clock net "clk_regs" -[INFO CTS-0099] Sinks 2254 -[INFO CTS-0100] Leaf buffers 227 -[INFO CTS-0101] Average sink wire length 4121.94 um -[INFO CTS-0102] Path depth 17 - 17 -[INFO CTS-0207] Dummy loads inserted 4 +[INFO CTS-0099] Sinks 2296 +[INFO CTS-0100] Leaf buffers 136 +[INFO CTS-0101] Average sink wire length 3917.23 um +[INFO CTS-0102] Path depth 15 - 15 +[INFO CTS-0207] Dummy loads inserted 46 [INFO CTS-0033] Balancing latency for clock clk [INFO CTS-0036] inserted 3 delay buffers [INFO CTS-0037] Total number of delay buffers: 3 [INFO RSZ-0058] Using max wire length 693um. -[INFO RSZ-0047] Found 41 long wires. -[INFO RSZ-0048] Inserted 165 buffers in 41 nets. +[INFO RSZ-0047] Found 35 long wires. +[INFO RSZ-0048] Inserted 204 buffers in 35 nets. Placement Analysis --------------------------------- -total displacement 4186.7 u -average displacement 1.3 u -max displacement 143.4 u -original HPWL 192698.4 u -legalized HPWL 193625.0 u -delta HPWL 0 % +total displacement 4400.8 u +average displacement 1.4 u +max displacement 137.7 u +original HPWL 182505.7 u +legalized HPWL 183634.8 u +delta HPWL 1 % Clock clk 1.03 source latency inst_5_4/clk ^ diff --git a/src/cts/test/array_no_blockages.ok b/src/cts/test/array_no_blockages.ok index 5aaed1af14f..ae105d1b8c1 100644 --- a/src/cts/test/array_no_blockages.ok +++ b/src/cts/test/array_no_blockages.ok @@ -49,54 +49,49 @@ [INFO CTS-0201] 225 blockages from hard placement blockages and placed macros will be used. [INFO CTS-0027] Generating H-Tree topology for net clk_regs. [INFO CTS-0028] Total number of sinks: 2250. -[INFO CTS-0029] Register sinks will be clustered in groups of up to 20 and with maximum cluster diameter of 100.0 um. +[INFO CTS-0059] Register sinks will be clustered with maximum cluster diameter of 100.0 um and based on buffer max cap. [INFO CTS-0030] Number of static layers: 0. [INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). -[INFO CTS-0204] A clustering solution was found from clustering size of 10 and clustering diameter of 100. +[INFO CTS-0204] A clustering solution was found from clustering size of 30 and clustering diameter of 100. [INFO CTS-0205] Better solution may be possible if either -sink_clustering_size, -sink_clustering_max_diameter, or both options are omitted to enable automatic clustering. -[INFO CTS-0019] Total number of sinks after clustering: 227. -[INFO CTS-0024] Normalized sink region: [(189.626, 2.21643), (661.055, 670.416)]. +[INFO CTS-0019] Total number of sinks after clustering: 136. +[INFO CTS-0024] Normalized sink region: [(189.626, 2.41643), (661.055, 670.416)]. [INFO CTS-0025] Width: 471.4286. -[INFO CTS-0026] Height: 668.2000. +[INFO CTS-0026] Height: 668.0000. Level 1 Direction: Vertical - Sinks per sub-region: 114 - Sub-region size: 471.4286 X 334.1000 -[INFO CTS-0034] Segment length (rounded): 168. + Sinks per sub-region: 68 + Sub-region size: 471.4286 X 334.0000 +[INFO CTS-0034] Segment length (rounded): 166. Level 2 Direction: Horizontal - Sinks per sub-region: 57 - Sub-region size: 235.7143 X 334.1000 + Sinks per sub-region: 34 + Sub-region size: 235.7143 X 334.0000 [INFO CTS-0034] Segment length (rounded): 118. Level 3 Direction: Vertical - Sinks per sub-region: 29 - Sub-region size: 235.7143 X 167.0500 + Sinks per sub-region: 17 + Sub-region size: 235.7143 X 167.0000 [INFO CTS-0034] Segment length (rounded): 84. Level 4 Direction: Horizontal - Sinks per sub-region: 15 - Sub-region size: 117.8572 X 167.0500 + Sinks per sub-region: 9 + Sub-region size: 117.8572 X 167.0000 [INFO CTS-0034] Segment length (rounded): 58. - Level 5 - Direction: Vertical - Sinks per sub-region: 8 - Sub-region size: 117.8572 X 83.5250 -[INFO CTS-0034] Segment length (rounded): 42. [INFO CTS-0032] Stop criterion found. Max number of sinks is 15. -[INFO CTS-0035] Number of sinks covered: 227. +[INFO CTS-0035] Number of sinks covered: 136. [INFO CTS-0018] Created 190 clock buffers. [INFO CTS-0012] Minimum number of buffers in the clock path: 16. [INFO CTS-0013] Maximum number of buffers in the clock path: 17. [INFO CTS-0015] Created 190 clock nets. [INFO CTS-0016] Fanout distribution for the current clock = 2:103, 6:1, 7:6, 8:7, 9:2.. [INFO CTS-0017] Max level of the clock tree: 4. -[INFO CTS-0018] Created 366 clock buffers. -[INFO CTS-0012] Minimum number of buffers in the clock path: 17. -[INFO CTS-0013] Maximum number of buffers in the clock path: 17. -[INFO CTS-0015] Created 366 clock nets. -[INFO CTS-0016] Fanout distribution for the current clock = 2:1, 4:3, 5:9, 6:5, 7:4, 8:3, 9:4, 10:230.. -[INFO CTS-0017] Max level of the clock tree: 5. +[INFO CTS-0018] Created 211 clock buffers. +[INFO CTS-0012] Minimum number of buffers in the clock path: 15. +[INFO CTS-0013] Maximum number of buffers in the clock path: 15. +[INFO CTS-0015] Created 211 clock nets. +[INFO CTS-0016] Fanout distribution for the current clock = 4:1, 5:2, 6:3, 7:2, 8:1, 9:5, 10:44, 11:1, 12:3, 20:90.. +[INFO CTS-0017] Max level of the clock tree: 4. [INFO CTS-0098] Clock net "clk" [INFO CTS-0099] Sinks 225 [INFO CTS-0100] Leaf buffers 103 @@ -104,24 +99,24 @@ [INFO CTS-0102] Path depth 16 - 17 [INFO CTS-0207] Dummy loads inserted 0 [INFO CTS-0098] Clock net "clk_regs" -[INFO CTS-0099] Sinks 2254 -[INFO CTS-0100] Leaf buffers 227 -[INFO CTS-0101] Average sink wire length 4117.74 um -[INFO CTS-0102] Path depth 17 - 17 -[INFO CTS-0207] Dummy loads inserted 4 +[INFO CTS-0099] Sinks 2296 +[INFO CTS-0100] Leaf buffers 136 +[INFO CTS-0101] Average sink wire length 3905.49 um +[INFO CTS-0102] Path depth 15 - 15 +[INFO CTS-0207] Dummy loads inserted 46 [INFO CTS-0033] Balancing latency for clock clk -[INFO CTS-0036] inserted 4 delay buffers -[INFO CTS-0037] Total number of delay buffers: 4 +[INFO CTS-0036] inserted 3 delay buffers +[INFO CTS-0037] Total number of delay buffers: 3 [INFO RSZ-0058] Using max wire length 693um. -[INFO RSZ-0047] Found 42 long wires. -[INFO RSZ-0048] Inserted 166 buffers in 42 nets. +[INFO RSZ-0047] Found 35 long wires. +[INFO RSZ-0048] Inserted 201 buffers in 35 nets. Placement Analysis --------------------------------- -total displacement 4302.0 u +total displacement 4102.5 u average displacement 1.3 u -max displacement 142.4 u -original HPWL 193675.5 u -legalized HPWL 194702.8 u +max displacement 136.4 u +original HPWL 182918.1 u +legalized HPWL 183922.4 u delta HPWL 1 % Clock clk diff --git a/src/cts/test/array_repair_clock_nets.ok b/src/cts/test/array_repair_clock_nets.ok index 02d83445d08..0149f3d7ff8 100644 --- a/src/cts/test/array_repair_clock_nets.ok +++ b/src/cts/test/array_repair_clock_nets.ok @@ -50,54 +50,49 @@ [INFO CTS-0201] 225 blockages from hard placement blockages and placed macros will be used. [INFO CTS-0027] Generating H-Tree topology for net clk_regs. [INFO CTS-0028] Total number of sinks: 2250. -[INFO CTS-0029] Register sinks will be clustered in groups of up to 20 and with maximum cluster diameter of 100.0 um. +[INFO CTS-0059] Register sinks will be clustered with maximum cluster diameter of 100.0 um and based on buffer max cap. [INFO CTS-0030] Number of static layers: 0. [INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). -[INFO CTS-0204] A clustering solution was found from clustering size of 10 and clustering diameter of 100. +[INFO CTS-0204] A clustering solution was found from clustering size of 30 and clustering diameter of 100. [INFO CTS-0205] Better solution may be possible if either -sink_clustering_size, -sink_clustering_max_diameter, or both options are omitted to enable automatic clustering. -[INFO CTS-0019] Total number of sinks after clustering: 227. -[INFO CTS-0024] Normalized sink region: [(189.626, 2.21643), (661.055, 670.416)]. +[INFO CTS-0019] Total number of sinks after clustering: 136. +[INFO CTS-0024] Normalized sink region: [(189.626, 2.41643), (661.055, 670.416)]. [INFO CTS-0025] Width: 471.4286. -[INFO CTS-0026] Height: 668.2000. +[INFO CTS-0026] Height: 668.0000. Level 1 Direction: Vertical - Sinks per sub-region: 114 - Sub-region size: 471.4286 X 334.1000 -[INFO CTS-0034] Segment length (rounded): 168. + Sinks per sub-region: 68 + Sub-region size: 471.4286 X 334.0000 +[INFO CTS-0034] Segment length (rounded): 166. Level 2 Direction: Horizontal - Sinks per sub-region: 57 - Sub-region size: 235.7143 X 334.1000 + Sinks per sub-region: 34 + Sub-region size: 235.7143 X 334.0000 [INFO CTS-0034] Segment length (rounded): 118. Level 3 Direction: Vertical - Sinks per sub-region: 29 - Sub-region size: 235.7143 X 167.0500 + Sinks per sub-region: 17 + Sub-region size: 235.7143 X 167.0000 [INFO CTS-0034] Segment length (rounded): 84. Level 4 Direction: Horizontal - Sinks per sub-region: 15 - Sub-region size: 117.8572 X 167.0500 + Sinks per sub-region: 9 + Sub-region size: 117.8572 X 167.0000 [INFO CTS-0034] Segment length (rounded): 58. - Level 5 - Direction: Vertical - Sinks per sub-region: 8 - Sub-region size: 117.8572 X 83.5250 -[INFO CTS-0034] Segment length (rounded): 42. [INFO CTS-0032] Stop criterion found. Max number of sinks is 15. -[INFO CTS-0035] Number of sinks covered: 227. +[INFO CTS-0035] Number of sinks covered: 136. [INFO CTS-0018] Created 190 clock buffers. [INFO CTS-0012] Minimum number of buffers in the clock path: 16. [INFO CTS-0013] Maximum number of buffers in the clock path: 17. [INFO CTS-0015] Created 190 clock nets. [INFO CTS-0016] Fanout distribution for the current clock = 2:103, 6:1, 7:6, 8:7, 9:2.. [INFO CTS-0017] Max level of the clock tree: 4. -[INFO CTS-0018] Created 366 clock buffers. -[INFO CTS-0012] Minimum number of buffers in the clock path: 17. -[INFO CTS-0013] Maximum number of buffers in the clock path: 17. -[INFO CTS-0015] Created 366 clock nets. -[INFO CTS-0016] Fanout distribution for the current clock = 2:1, 4:3, 5:9, 6:5, 7:4, 8:3, 9:4, 10:230.. -[INFO CTS-0017] Max level of the clock tree: 5. +[INFO CTS-0018] Created 211 clock buffers. +[INFO CTS-0012] Minimum number of buffers in the clock path: 15. +[INFO CTS-0013] Maximum number of buffers in the clock path: 15. +[INFO CTS-0015] Created 211 clock nets. +[INFO CTS-0016] Fanout distribution for the current clock = 4:1, 5:2, 6:3, 7:2, 8:1, 9:5, 10:44, 11:1, 12:3, 20:90.. +[INFO CTS-0017] Max level of the clock tree: 4. [INFO CTS-0098] Clock net "clk" [INFO CTS-0099] Sinks 225 [INFO CTS-0100] Leaf buffers 103 @@ -105,43 +100,42 @@ [INFO CTS-0102] Path depth 16 - 17 [INFO CTS-0207] Dummy loads inserted 0 [INFO CTS-0098] Clock net "clk_regs" -[INFO CTS-0099] Sinks 2254 -[INFO CTS-0100] Leaf buffers 227 -[INFO CTS-0101] Average sink wire length 4121.94 um -[INFO CTS-0102] Path depth 17 - 17 -[INFO CTS-0207] Dummy loads inserted 4 -[INFO RSZ-0047] Found 38 long wires. -[INFO RSZ-0048] Inserted 160 buffers in 38 nets. +[INFO CTS-0099] Sinks 2296 +[INFO CTS-0100] Leaf buffers 136 +[INFO CTS-0101] Average sink wire length 3917.23 um +[INFO CTS-0102] Path depth 15 - 15 +[INFO CTS-0207] Dummy loads inserted 46 +[INFO RSZ-0047] Found 32 long wires. +[INFO RSZ-0048] Inserted 199 buffers in 32 nets. [INFO CTS-0033] Balancing latency for clock clk -[INFO CTS-0036] inserted 0 delay buffers +[INFO CTS-0036] inserted 1 delay buffers +[INFO CTS-0037] Total number of delay buffers: 1 Total number of Clock Roots: 2. -Total number of Buffers Inserted: 556. -Total number of Clock Subnets: 556. +Total number of Buffers Inserted: 401. +Total number of Clock Subnets: 401. Total number of Sinks: 2475. Cells used: - BUF_X1: 20 - BUF_X16: 12 - BUF_X2: 7 - BUF_X32: 5 - BUF_X4: 600 - BUF_X8: 73 + BUF_X1: 41 + BUF_X16: 10 + BUF_X2: 8 + BUF_X32: 7 + BUF_X4: 451 + BUF_X8: 85 Dummys used: - BUF_X4: 2 - INV_X1: 1 - INV_X4: 1 + INV_X8: 46 [INFO RSZ-0058] Using max wire length 693um. Placement Analysis --------------------------------- -total displacement 4309.2 u -average displacement 1.3 u -max displacement 143.4 u -original HPWL 189421.9 u -legalized HPWL 190353.6 u -delta HPWL 0 % +total displacement 4524.1 u +average displacement 1.4 u +max displacement 137.7 u +original HPWL 179448.7 u +legalized HPWL 180579.8 u +delta HPWL 1 % Clock clk - 1.08 source latency inst_5_4/clk ^ - -1.23 target latency inst_6_4/clk ^ + 1.07 source latency inst_5_4/clk ^ + -1.22 target latency inst_6_4/clk ^ 0.00 CRPR -------------- -0.15 setup skew @@ -164,25 +158,25 @@ Path Type: max 0.06 0.29 ^ wire5/Z (BUF_X32) 0.04 0.33 ^ wire4/Z (BUF_X32) 0.06 0.39 ^ wire3/Z (BUF_X32) - 0.07 0.45 ^ wire1/Z (BUF_X2) - 0.04 0.50 ^ clkbuf_0_clk/Z (BUF_X4) - 0.04 0.54 ^ clkbuf_1_0_0_clk/Z (BUF_X4) + 0.06 0.45 ^ wire1/Z (BUF_X2) + 0.04 0.49 ^ clkbuf_0_clk/Z (BUF_X4) + 0.04 0.53 ^ clkbuf_1_0_0_clk/Z (BUF_X4) 0.04 0.57 ^ clkbuf_1_0_1_clk/Z (BUF_X4) 0.04 0.61 ^ clkbuf_1_0_2_clk/Z (BUF_X4) 0.03 0.64 ^ clkbuf_1_0_3_clk/Z (BUF_X4) 0.04 0.68 ^ clkbuf_1_0_4_clk/Z (BUF_X4) - 0.03 0.72 ^ clkbuf_2_0_0_clk/Z (BUF_X4) + 0.03 0.71 ^ clkbuf_2_0_0_clk/Z (BUF_X4) 0.03 0.75 ^ clkbuf_2_0_1_clk/Z (BUF_X4) - 0.03 0.79 ^ clkbuf_2_0_2_clk/Z (BUF_X4) + 0.03 0.78 ^ clkbuf_2_0_2_clk/Z (BUF_X4) 0.03 0.82 ^ clkbuf_2_0_3_clk/Z (BUF_X4) 0.04 0.86 ^ clkbuf_2_0_4_clk/Z (BUF_X4) 0.03 0.89 ^ clkbuf_3_0_0_clk/Z (BUF_X4) - 0.03 0.93 ^ clkbuf_3_0_1_clk/Z (BUF_X4) + 0.03 0.92 ^ clkbuf_3_0_1_clk/Z (BUF_X4) 0.03 0.96 ^ clkbuf_3_0_2_clk/Z (BUF_X4) 0.04 1.00 ^ clkbuf_4_0_0_clk/Z (BUF_X4) 0.05 1.05 ^ clkbuf_4_0_1_clk/Z (BUF_X4) - 0.04 1.10 ^ wire15/Z (BUF_X8) - 0.05 1.15 ^ load_slew12/Z (BUF_X1) + 0.04 1.09 ^ wire15/Z (BUF_X8) + 0.05 1.14 ^ load_slew12/Z (BUF_X1) 0.03 1.18 ^ clkbuf_leaf_0_clk/Z (BUF_X4) 0.00 1.18 ^ inst_1_1/clk (array_tile) 0.21 1.39 ^ inst_1_1/e_out (array_tile) @@ -200,31 +194,31 @@ Path Type: max 0.06 5.29 ^ wire5/Z (BUF_X32) 0.04 5.33 ^ wire4/Z (BUF_X32) 0.06 5.39 ^ wire3/Z (BUF_X32) - 0.07 5.45 ^ wire1/Z (BUF_X2) - 0.04 5.50 ^ clkbuf_0_clk/Z (BUF_X4) - 0.04 5.54 ^ clkbuf_1_0_0_clk/Z (BUF_X4) + 0.06 5.45 ^ wire1/Z (BUF_X2) + 0.04 5.49 ^ clkbuf_0_clk/Z (BUF_X4) + 0.04 5.53 ^ clkbuf_1_0_0_clk/Z (BUF_X4) 0.04 5.57 ^ clkbuf_1_0_1_clk/Z (BUF_X4) 0.04 5.61 ^ clkbuf_1_0_2_clk/Z (BUF_X4) 0.03 5.64 ^ clkbuf_1_0_3_clk/Z (BUF_X4) 0.04 5.68 ^ clkbuf_1_0_4_clk/Z (BUF_X4) - 0.03 5.72 ^ clkbuf_2_0_0_clk/Z (BUF_X4) + 0.03 5.71 ^ clkbuf_2_0_0_clk/Z (BUF_X4) 0.03 5.75 ^ clkbuf_2_0_1_clk/Z (BUF_X4) - 0.03 5.79 ^ clkbuf_2_0_2_clk/Z (BUF_X4) + 0.03 5.78 ^ clkbuf_2_0_2_clk/Z (BUF_X4) 0.03 5.82 ^ clkbuf_2_0_3_clk/Z (BUF_X4) 0.04 5.86 ^ clkbuf_2_0_4_clk/Z (BUF_X4) 0.03 5.89 ^ clkbuf_3_0_0_clk/Z (BUF_X4) - 0.03 5.93 ^ clkbuf_3_0_1_clk/Z (BUF_X4) + 0.03 5.92 ^ clkbuf_3_0_1_clk/Z (BUF_X4) 0.03 5.96 ^ clkbuf_3_0_2_clk/Z (BUF_X4) 0.04 6.00 ^ clkbuf_4_0_0_clk/Z (BUF_X4) 0.05 6.05 ^ clkbuf_4_0_1_clk/Z (BUF_X4) - 0.04 6.09 ^ load_slew19/Z (BUF_X8) - 0.03 6.12 ^ load_slew17/Z (BUF_X1) - 0.00 6.12 ^ inst_2_1/clk (array_tile) - 0.00 6.12 clock reconvergence pessimism - -0.05 6.07 library setup time - 6.07 data required time + 0.04 6.08 ^ load_slew19/Z (BUF_X8) + 0.03 6.11 ^ load_slew17/Z (BUF_X1) + 0.00 6.11 ^ inst_2_1/clk (array_tile) + 0.00 6.11 clock reconvergence pessimism + -0.05 6.06 library setup time + 6.06 data required time --------------------------------------------------------- - 6.07 data required time + 6.06 data required time -1.39 data arrival time --------------------------------------------------------- 4.67 slack (MET) @@ -248,29 +242,29 @@ Path Type: max 0.06 0.29 ^ wire5/Z (BUF_X32) 0.04 0.33 ^ wire4/Z (BUF_X32) 0.06 0.39 ^ wire3/Z (BUF_X32) - 0.07 0.45 ^ wire1/Z (BUF_X2) - 0.04 0.50 ^ clkbuf_0_clk/Z (BUF_X4) - 0.04 0.54 ^ clkbuf_1_0_0_clk/Z (BUF_X4) + 0.06 0.45 ^ wire1/Z (BUF_X2) + 0.04 0.49 ^ clkbuf_0_clk/Z (BUF_X4) + 0.04 0.53 ^ clkbuf_1_0_0_clk/Z (BUF_X4) 0.04 0.57 ^ clkbuf_1_0_1_clk/Z (BUF_X4) 0.04 0.61 ^ clkbuf_1_0_2_clk/Z (BUF_X4) 0.03 0.64 ^ clkbuf_1_0_3_clk/Z (BUF_X4) 0.04 0.68 ^ clkbuf_1_0_4_clk/Z (BUF_X4) - 0.03 0.72 ^ clkbuf_2_0_0_clk/Z (BUF_X4) + 0.03 0.71 ^ clkbuf_2_0_0_clk/Z (BUF_X4) 0.03 0.75 ^ clkbuf_2_0_1_clk/Z (BUF_X4) - 0.03 0.79 ^ clkbuf_2_0_2_clk/Z (BUF_X4) + 0.03 0.78 ^ clkbuf_2_0_2_clk/Z (BUF_X4) 0.03 0.82 ^ clkbuf_2_0_3_clk/Z (BUF_X4) 0.04 0.86 ^ clkbuf_2_0_4_clk/Z (BUF_X4) 0.03 0.89 ^ clkbuf_3_0_0_clk/Z (BUF_X4) - 0.03 0.93 ^ clkbuf_3_0_1_clk/Z (BUF_X4) + 0.03 0.92 ^ clkbuf_3_0_1_clk/Z (BUF_X4) 0.03 0.96 ^ clkbuf_3_0_2_clk/Z (BUF_X4) 0.04 1.00 ^ clkbuf_4_0_0_clk/Z (BUF_X4) 0.05 1.05 ^ clkbuf_4_0_1_clk/Z (BUF_X4) - 0.04 1.09 ^ load_slew19/Z (BUF_X8) - 0.03 1.12 ^ load_slew17/Z (BUF_X1) - 0.00 1.12 ^ inst_2_1/clk (array_tile) - 0.21 1.33 ^ inst_2_1/e_out (array_tile) - 0.00 1.33 ^ inst_3_1/w_in (array_tile) - 1.33 data arrival time + 0.04 1.08 ^ load_slew19/Z (BUF_X8) + 0.03 1.11 ^ load_slew17/Z (BUF_X1) + 0.00 1.11 ^ inst_2_1/clk (array_tile) + 0.21 1.32 ^ inst_2_1/e_out (array_tile) + 0.00 1.32 ^ inst_3_1/w_in (array_tile) + 1.32 data arrival time 5.00 5.00 clock clk (rise edge) 0.00 5.00 clock source latency @@ -283,33 +277,33 @@ Path Type: max 0.06 5.29 ^ wire5/Z (BUF_X32) 0.04 5.33 ^ wire4/Z (BUF_X32) 0.06 5.39 ^ wire3/Z (BUF_X32) - 0.07 5.45 ^ wire1/Z (BUF_X2) - 0.04 5.50 ^ clkbuf_0_clk/Z (BUF_X4) - 0.04 5.54 ^ clkbuf_1_0_0_clk/Z (BUF_X4) + 0.06 5.45 ^ wire1/Z (BUF_X2) + 0.04 5.49 ^ clkbuf_0_clk/Z (BUF_X4) + 0.04 5.53 ^ clkbuf_1_0_0_clk/Z (BUF_X4) 0.04 5.57 ^ clkbuf_1_0_1_clk/Z (BUF_X4) 0.04 5.61 ^ clkbuf_1_0_2_clk/Z (BUF_X4) 0.03 5.64 ^ clkbuf_1_0_3_clk/Z (BUF_X4) 0.04 5.68 ^ clkbuf_1_0_4_clk/Z (BUF_X4) - 0.03 5.72 ^ clkbuf_2_0_0_clk/Z (BUF_X4) + 0.03 5.71 ^ clkbuf_2_0_0_clk/Z (BUF_X4) 0.03 5.75 ^ clkbuf_2_0_1_clk/Z (BUF_X4) - 0.03 5.79 ^ clkbuf_2_0_2_clk/Z (BUF_X4) + 0.03 5.78 ^ clkbuf_2_0_2_clk/Z (BUF_X4) 0.03 5.82 ^ clkbuf_2_0_3_clk/Z (BUF_X4) 0.04 5.86 ^ clkbuf_2_0_4_clk/Z (BUF_X4) 0.03 5.89 ^ clkbuf_3_0_0_clk/Z (BUF_X4) - 0.03 5.93 ^ clkbuf_3_0_1_clk/Z (BUF_X4) + 0.03 5.92 ^ clkbuf_3_0_1_clk/Z (BUF_X4) 0.03 5.96 ^ clkbuf_3_0_2_clk/Z (BUF_X4) 0.04 6.00 ^ clkbuf_4_0_0_clk/Z (BUF_X4) 0.05 6.05 ^ clkbuf_4_0_1_clk/Z (BUF_X4) - 0.04 6.09 ^ load_slew19/Z (BUF_X8) - 0.04 6.13 ^ wire18/Z (BUF_X4) - 0.04 6.17 ^ clkbuf_leaf_118_clk/Z (BUF_X4) - 0.00 6.17 ^ inst_3_1/clk (array_tile) - 0.00 6.17 clock reconvergence pessimism - -0.05 6.12 library setup time - 6.12 data required time + 0.04 6.08 ^ load_slew19/Z (BUF_X8) + 0.04 6.12 ^ wire18/Z (BUF_X4) + 0.04 6.16 ^ clkbuf_leaf_118_clk/Z (BUF_X4) + 0.00 6.16 ^ inst_3_1/clk (array_tile) + 0.00 6.16 clock reconvergence pessimism + -0.05 6.11 library setup time + 6.11 data required time --------------------------------------------------------- - 6.12 data required time - -1.33 data arrival time + 6.11 data required time + -1.32 data arrival time --------------------------------------------------------- 4.79 slack (MET) diff --git a/src/cts/test/check_max_fanout3.ok b/src/cts/test/check_max_fanout3.ok index e7d13923344..50e772d5e64 100644 --- a/src/cts/test/check_max_fanout3.ok +++ b/src/cts/test/check_max_fanout3.ok @@ -16,11 +16,12 @@ [INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used. [INFO CTS-0027] Generating H-Tree topology for net clk. [INFO CTS-0028] Total number of sinks: 300. -[INFO CTS-0090] Sinks will be clustered based on buffer max cap. +[INFO CTS-0060] Register sinks will be clustered in groups of up to 8 and based on buffer max cap. [INFO CTS-0030] Number of static layers: 1. [INFO CTS-0020] Wire segment unit: 18900 dbu (18 um). [INFO CTS-0021] Distance between buffers: 2 units (100 um). -[INFO CTS-0206] Best clustering solution was found from clustering size of 8 and clustering diameter of 50. +[INFO CTS-0204] A clustering solution was found from clustering size of 8 and clustering diameter of 50. +[INFO CTS-0205] Better solution may be possible if either -sink_clustering_size, -sink_clustering_max_diameter, or both options are omitted to enable automatic clustering. [INFO CTS-0019] Total number of sinks after clustering: 50. [INFO CTS-0024] Normalized sink region: [(0.808748, 0.583104), (10.0189, 9.59732)]. [INFO CTS-0025] Width: 9.2102. diff --git a/src/cts/test/gated_clock1.ok b/src/cts/test/gated_clock1.ok index 39541cca729..c4753b48e6b 100644 --- a/src/cts/test/gated_clock1.ok +++ b/src/cts/test/gated_clock1.ok @@ -59,7 +59,7 @@ [INFO CTS-0030] Number of static layers: 1. [INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). [INFO CTS-0021] Distance between buffers: 7 units (100 um). -[INFO CTS-0206] Best clustering solution was found from clustering size of 10 and clustering diameter of 50. +[INFO CTS-0206] Best clustering solution was found from clustering size of 30 and clustering diameter of 50. [INFO CTS-0019] Total number of sinks after clustering: 38. [INFO CTS-0024] Normalized sink region: [(1.425, 0.912143), (13.2981, 11.6662)]. [INFO CTS-0025] Width: 11.8731. diff --git a/src/cts/test/inverters.ok b/src/cts/test/inverters.ok index ff35d4083ba..5b64f8377af 100644 --- a/src/cts/test/inverters.ok +++ b/src/cts/test/inverters.ok @@ -40,7 +40,7 @@ [INFO CTS-0030] Number of static layers: 1. [INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). [INFO CTS-0021] Distance between buffers: 7 units (100 um). -[INFO CTS-0206] Best clustering solution was found from clustering size of 20 and clustering diameter of 50. +[INFO CTS-0206] Best clustering solution was found from clustering size of 30 and clustering diameter of 50. [INFO CTS-0019] Total number of sinks after clustering: 39. [INFO CTS-0024] Normalized sink region: [(1.425, 0.912143), (13.3916, 11.6662)]. [INFO CTS-0025] Width: 11.9666. diff --git a/src/cts/test/skip_nets.ok b/src/cts/test/skip_nets.ok index 93c1ae1059d..9d646c173c5 100644 --- a/src/cts/test/skip_nets.ok +++ b/src/cts/test/skip_nets.ok @@ -20,7 +20,7 @@ CTS config: -sink_buffer_max_cap_derate: 0.01 -sink_clustering_levels: 0 -sink_clustering_max_diameter: 50.0 --sink_clustering_size: 20 +-sink_clustering_size: 30 -skip_nets: gclk1 gclk3 -tree_buf: undefined -wire_unit: 20 diff --git a/test/aes_nangate45.metrics b/test/aes_nangate45.metrics index 0c4b30edc4a..0b3314a508c 100644 --- a/test/aes_nangate45.metrics +++ b/test/aes_nangate45.metrics @@ -11,42 +11,44 @@ "RSZ::max_slew_slack": "25.182229343163016", "RSZ::max_fanout_slack": "100.0", "RSZ::max_capacitance_slack": "20.783033335112332", - "design__instance__displacement__total": 54.656, - "design__instance__displacement__mean": 0.0025, - "design__instance__displacement__max": 2.0965, - "route__wirelength__estimated": 503297, - "design__instance__count__setup_buffer": 1080, - "design__instance__count__hold_buffer": 291, - "RSZ::worst_slack_min": "6.911138523751946e-6", - "RSZ::worst_slack_max": "-0.28506220413249445", - "RSZ::tns_max": "-25.84096743060745", - "RSZ::hold_buffer_count": "291", - "design__instance__displacement__total": 2587.75, - "design__instance__displacement__mean": 0.123, - "design__instance__displacement__max": 3.8875, - "route__wirelength__estimated": 533343, - "DPL::utilization": "2.9", - "DPL::design_area": "25960", - "route__net": 17933, + "design__instance__displacement__total": 110.626, + "design__instance__displacement__mean": 0.0055, + "design__instance__displacement__max": 2.165, + "route__wirelength__estimated": 504208, + "design__instance__count__setup_buffer": 851, + "design__instance__count__hold_buffer": 305, + "RSZ::worst_slack_min": "0.00030178638220383495", + "RSZ::worst_slack_max": "-0.29870717855795126", + "RSZ::tns_max": "-29.144767424368", + "RSZ::hold_buffer_count": "305", + "design__instance__displacement__total": 2090.75, + "design__instance__displacement__mean": 0.1, + "design__instance__displacement__max": 4.7125, + "route__wirelength__estimated": 529321, + "DPL::utilization": "2.8", + "DPL::design_area": "25302", + "route__net": 17747, "route__net__special": 2, - "global_route__vias": 159015, - "global_route__wirelength": 807188, + "global_route__vias": 158192, + "global_route__wirelength": 803073, "grt__antenna_diodes_count": 0, "grt__antenna__violating__nets": 0, "grt__antenna__violating__pins": 0, "GRT::ANT::errors": "0", - "route__drc_errors__iter:0": 3165, - "route__wirelength__iter:0": 636204, - "route__drc_errors__iter:1": 531, - "route__wirelength__iter:1": 633932, - "route__drc_errors__iter:2": 337, - "route__wirelength__iter:2": 633556, - "route__drc_errors__iter:3": 0, - "route__wirelength__iter:3": 633579, + "route__drc_errors__iter:0": 3113, + "route__wirelength__iter:0": 632541, + "route__drc_errors__iter:1": 526, + "route__wirelength__iter:1": 630649, + "route__drc_errors__iter:2": 296, + "route__wirelength__iter:2": 630256, + "route__drc_errors__iter:3": 3, + "route__wirelength__iter:3": 630236, + "route__drc_errors__iter:4": 0, + "route__wirelength__iter:4": 630237, "route__drc_errors": 0, - "route__wirelength": 633579, - "route__vias": 145377, - "route__vias__singlecut": 145377, + "route__wirelength": 630237, + "route__vias": 144692, + "route__vias__singlecut": 144692, "route__vias__multicut": 0, "DRT::drv": "0", "drt__repair_antennas__pre_repair__antenna__violating__nets": 0, @@ -57,13 +59,13 @@ "design__violations": 0, "timing__drv__floating__nets": 0, "timing__drv__floating__pins": 0, - "DRT::worst_slack_min": "-0.013018295143695615", - "DRT::worst_slack_max": "-0.3827100966682317", - "DRT::tns_max": "-36.77157882267284", - "DRT::clock_skew": "0.029945199945066163", - "DRT::max_slew_slack": "2.492123291115565", + "DRT::worst_slack_min": "-0.004841321924829239", + "DRT::worst_slack_max": "-0.35594461718898407", + "DRT::tns_max": "-40.58552719885505", + "DRT::clock_skew": "0.05473537056303519", + "DRT::max_slew_slack": "19.001998204970512", "DRT::max_fanout_slack": "100.0", - "DRT::max_capacitance_slack": "-26.681076374956042", + "DRT::max_capacitance_slack": "-31.805323115465693", "DRT::clock_period": "0.810900", "flow__warnings__count": 9, "flow__errors__count": 0, diff --git a/test/aes_nangate45.metrics_limits b/test/aes_nangate45.metrics_limits index c138842e91f..fe8ce736d65 100644 --- a/test/aes_nangate45.metrics_limits +++ b/test/aes_nangate45.metrics_limits @@ -1,23 +1,23 @@ { "IFP::instance_count" : "20110.8" - ,"DPL::design_area" : "31152.0" - ,"DPL::utilization" : "3.48" + ,"DPL::design_area" : "30362.399999999998" + ,"DPL::utilization" : "3.36" ,"RSZ::repair_design_buffer_count" : "1083" ,"RSZ::max_slew_slack" : "0" ,"RSZ::max_capacitance_slack" : "0" ,"RSZ::max_fanout_slack" : "0" - ,"RSZ::worst_slack_min" : "-0.08108308886147625" - ,"RSZ::worst_slack_max" : "-0.36615220413249444" - ,"RSZ::tns_max" : "-161.73969843060746" - ,"RSZ::hold_buffer_count" : "349" + ,"RSZ::worst_slack_min" : "-0.08078821361779616" + ,"RSZ::worst_slack_max" : "-0.37979717855795125" + ,"RSZ::tns_max" : "-165.043498424368" + ,"RSZ::hold_buffer_count" : "366" ,"GRT::ANT::errors" : "0" ,"DRT::drv" : "0" - ,"DRT::worst_slack_min" : "-0.0941082951436956" - ,"DRT::worst_slack_max" : "-0.4638000966682317" - ,"DRT::tns_max" : "-172.67030982267283" - ,"DRT::clock_skew" : "0.0359342399340794" + ,"DRT::worst_slack_min" : "-0.08593132192482923" + ,"DRT::worst_slack_max" : "-0.43703461718898406" + ,"DRT::tns_max" : "-176.48425819885506" + ,"DRT::clock_skew" : "0.06568244467564223" ,"DRT::max_slew_slack" : "0" - ,"DRT::max_capacitance_slack" : "-32.017291649947246" + ,"DRT::max_capacitance_slack" : "-38.16638773855883" ,"DRT::max_fanout_slack" : "0" ,"DRT::clock_period" : "0.8109" ,"DRT::ANT::errors" : "0" diff --git a/test/jpeg_sky130hd.metrics b/test/jpeg_sky130hd.metrics index 27dfcc97c98..80f5eb575a6 100644 --- a/test/jpeg_sky130hd.metrics +++ b/test/jpeg_sky130hd.metrics @@ -11,94 +11,101 @@ "RSZ::max_slew_slack": "-49.76607149292421", "RSZ::max_fanout_slack": "100.0", "RSZ::max_capacitance_slack": "25.03487215931482", - "design__instance__displacement__total": 3500.63, - "design__instance__displacement__mean": 0.047, - "design__instance__displacement__max": 9.231, - "route__wirelength__estimated": 1.58903e+06, + "design__instance__displacement__total": 8649.47, + "design__instance__displacement__mean": 0.114, + "design__instance__displacement__max": 10.15, + "route__wirelength__estimated": 1.61408e+06, "design__instance__count__setup_buffer": 144, - "design__instance__count__hold_buffer": 27, - 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"drt__repair_antennas__iter_2__route__wirelength": 1812138, - "drt__repair_antennas__iter_2__route__vias": 314276, - "drt__repair_antennas__iter_2__route__vias__singlecut": 314276, + "drt__repair_antennas__iter_2__route__wirelength": 1829879, + "drt__repair_antennas__iter_2__route__vias": 320328, + "drt__repair_antennas__iter_2__route__vias__singlecut": 320328, "drt__repair_antennas__iter_2__route__vias__multicut": 0, "drt__repair_antennas__iter_2__antenna__violating__nets": 0, "drt__repair_antennas__iter_2__antenna__violating__pins": 0, @@ -108,15 +115,15 @@ "design__violations": 0, "timing__drv__floating__nets": 0, "timing__drv__floating__pins": 0, - "DRT::worst_slack_min": "0.03159694817445468", - "DRT::worst_slack_max": "-0.5302185507392476", - "DRT::tns_max": "-9.664038731685622", - "DRT::clock_skew": "0.5217104673717101", - "DRT::max_slew_slack": "-6.249916454129976", + "DRT::worst_slack_min": "0.03188227549985295", + "DRT::worst_slack_max": "-0.3406732770087571", + "DRT::tns_max": "-3.144455451689254", + "DRT::clock_skew": "0.4744440530291381", + "DRT::max_slew_slack": "-15.052755153286618", "DRT::max_fanout_slack": "100.0", - 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,"DPL::design_area" : "772842.0" - ,"DPL::utilization" : "35.4" + ,"DPL::design_area" : "781506.0" + ,"DPL::utilization" : "35.76" ,"RSZ::repair_design_buffer_count" : "672" ,"RSZ::max_slew_slack" : "-41.03741526603699" ,"RSZ::max_capacitance_slack" : "0" ,"RSZ::max_fanout_slack" : "0" - ,"RSZ::worst_slack_min" : "-0.6166812791967847" - ,"RSZ::worst_slack_max" : "-0.7479415078205778" - ,"RSZ::tns_max" : "-3185.487978769298" - ,"RSZ::hold_buffer_count" : "26" - ,"GRT::ANT::errors" : "0" + ,"RSZ::worst_slack_min" : "-0.6202719626045788" + ,"RSZ::worst_slack_max" : "-0.6354821294944188" + ,"RSZ::tns_max" : "-3185.0691600000005" + ,"RSZ::hold_buffer_count" : "22" + ,"GRT::ANT::errors" : "1" ,"DRT::drv" : "0" - ,"DRT::worst_slack_min" : "-0.6179339438708971" - ,"DRT::worst_slack_max" : "-1.482961573436981" - ,"DRT::tns_max" : "-3281.400582010328" - ,"DRT::clock_skew" : "0.44677156572204074" - ,"DRT::max_slew_slack" : "-45.4616904258728" + ,"DRT::worst_slack_min" : "-0.6341894967902897" + ,"DRT::worst_slack_max" : "-1.576329556091744" + ,"DRT::tns_max" : "-3301.8865386323587" + ,"DRT::clock_skew" : "0.38630273406860444" + ,"DRT::max_slew_slack" : "-38.634138107299805" ,"DRT::max_capacitance_slack" : "0" ,"DRT::max_fanout_slack" : "0" ,"DRT::clock_period" : "6.387" diff --git a/test/tinyRocket_nangate45.metrics b/test/tinyRocket_nangate45.metrics index ef3cb9c7210..634adb43933 100644 --- a/test/tinyRocket_nangate45.metrics +++ b/test/tinyRocket_nangate45.metrics @@ -12,46 +12,42 @@ "RSZ::max_slew_slack": "-109.46818761315569", "RSZ::max_fanout_slack": "100.0", "RSZ::max_capacitance_slack": "37.21016499704825", - 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"global_route__vias": 231928, - "global_route__wirelength": 784100, + "global_route__vias": 233365, + "global_route__wirelength": 791910, "grt__antenna_diodes_count": 0, "grt__antenna__violating__nets": 0, "grt__antenna__violating__pins": 0, "GRT::ANT::errors": "0", - "route__net": 28488, - "route__net__special": 2, - "route__drc_errors__iter:0": 2883, - "route__wirelength__iter:0": 583844, - "route__drc_errors__iter:1": 309, - "route__wirelength__iter:1": 581363, - "route__drc_errors__iter:2": 88, - "route__wirelength__iter:2": 581282, - "route__drc_errors__iter:3": 3, - "route__wirelength__iter:3": 581292, - "route__drc_errors__iter:4": 0, - "route__wirelength__iter:4": 581293, + "route__drc_errors__iter:0": 3123, + "route__wirelength__iter:0": 590955, + "route__drc_errors__iter:1": 316, + "route__wirelength__iter:1": 588509, + "route__drc_errors__iter:2": 91, + "route__wirelength__iter:2": 588353, + "route__drc_errors__iter:3": 0, + "route__wirelength__iter:3": 588361, "route__drc_errors": 0, - "route__wirelength": 581293, - "route__vias": 190143, - "route__vias__singlecut": 190143, + "route__wirelength": 588361, + "route__vias": 191318, + "route__vias__singlecut": 191318, "route__vias__multicut": 0, "DRT::drv": "0", "drt__repair_antennas__pre_repair__antenna__violating__nets": 0, @@ -62,18 +58,18 @@ "design__violations": 0, "timing__drv__floating__nets": 0, "timing__drv__floating__pins": 0, - "DRT::worst_slack_min": "0.07810963208429168", - "DRT::worst_slack_max": "-0.05850098349109418", - "DRT::tns_max": "-8.595445487548348", - "DRT::clock_skew": "0.044500293598487166", - "DRT::max_slew_slack": "-9.610012655873573", + "DRT::worst_slack_min": "0.07945160032547299", + "DRT::worst_slack_max": "-0.0714508472611741", + "DRT::tns_max": "-9.241735638348837", + "DRT::clock_skew": "0.03984376830133319", + "DRT::max_slew_slack": "-29.939898110535566", "DRT::max_fanout_slack": "100.0", - "DRT::max_capacitance_slack": "-90.80422167420537", + "DRT::max_capacitance_slack": "-128.39853880691453", "DRT::clock_period": "2.030000", - "flow__warnings__count": 12, + "flow__warnings__count": 13, "flow__errors__count": 0, "flow__warnings__count:GRT-0246": 1, - "flow__warnings__count:GRT-0273": 3, + "flow__warnings__count:GRT-0273": 4, "flow__warnings__count:GRT-0281": 1, "flow__warnings__count:IFP-0028": 1, "flow__warnings__count:ORD-0046": 5, diff --git a/test/tinyRocket_nangate45.metrics_limits b/test/tinyRocket_nangate45.metrics_limits index 3ee60c2ec24..c5eb7d9d958 100644 --- a/test/tinyRocket_nangate45.metrics_limits +++ b/test/tinyRocket_nangate45.metrics_limits @@ -1,23 +1,23 @@ { "IFP::instance_count" : "28653.6" - ,"DPL::design_area" : "64873.2" - ,"DPL::utilization" : "28.2" + ,"DPL::design_area" : "65448.0" + ,"DPL::utilization" : "28.439999999999998" ,"RSZ::repair_design_buffer_count" : "1298" ,"RSZ::max_slew_slack" : "-131.36182513578683" ,"RSZ::max_capacitance_slack" : "0" ,"RSZ::max_fanout_slack" : "0" - ,"RSZ::worst_slack_min" : "-0.12365219165247708" - ,"RSZ::worst_slack_max" : "-0.15923345281923934" + ,"RSZ::worst_slack_min" : "-0.12408441536597557" + ,"RSZ::worst_slack_max" : "-0.1668997650656991" ,"RSZ::tns_max" : "-484.72339999999997" ,"RSZ::hold_buffer_count" : "0" ,"GRT::ANT::errors" : "0" ,"DRT::drv" : "0" - ,"DRT::worst_slack_min" : "-0.1248903679157083" - ,"DRT::worst_slack_max" : "-0.2615009834910942" - ,"DRT::tns_max" : "-493.31884548754834" - ,"DRT::clock_skew" : "0.053400352318184595" - ,"DRT::max_slew_slack" : "-11.532015187048287" - ,"DRT::max_capacitance_slack" : "-108.96506600904644" + ,"DRT::worst_slack_min" : "-0.12354839967452699" + ,"DRT::worst_slack_max" : "-0.2744508472611741" + ,"DRT::tns_max" : "-493.9651356383488" + ,"DRT::clock_skew" : "0.047812521961599824" + ,"DRT::max_slew_slack" : "-35.92787773264268" + ,"DRT::max_capacitance_slack" : "-154.07824656829743" ,"DRT::max_fanout_slack" : "0" ,"DRT::clock_period" : "2.03" ,"DRT::ANT::errors" : "0"