AIE-ML LeNet tutorial: make run_emu hangs at Waiting for dma hls to complete... even with MTMODEL=false

[internet96]

Hi,

I am trying to run the Vitis-Tutorials 2025.2 AIE-ML LeNet tutorial:

AI_Engine_Development/AIE-ML/Design_Tutorials/03-AIE-ML-lenet_tutorial

I have successfully completed the build flow:

make kernels
make graph
make xsa
make application
make package

Then I launched hardware emulation from:

cd build/lenet_x1/hw_emu/package
export MTMODEL=false
./launch_hw_emu.sh

I also noticed the note in the tutorial:

The upgraded AI Engine model can exhibit some issues. As a temporary solution, set mtmodel as false by setenv MTMODEL false command before running hw_emu.

Since I am using bash, I used:

export MTMODEL=false
echo $MTMODEL

and confirmed that it prints:

false

After QEMU boots, I log in to the PetaLinux system, mount the SD card partition, and run the application:

sudo su
mount /dev/mmcblk0p1 /mnt
cd /mnt
./lenet_aie_xrt.elf a.xclbin

The xclbin seems to load successfully, and the AIE graph also seems to start:

Initializing ADF API...
Iteration : 1...
[drm] AIE create successfully finished.
[drm] xclbin ... successfully loaded to slot 0
XAIEFAL: INFO: Resource group Avail is created.
XAIEFAL: INFO: Resource group Static is created.
XAIEFAL: INFO: Resource group Generic is created.
Run Datamover
graph run
graph running...
Waiting for dma hls to complete...

However, the program stays forever at:

Waiting for dma hls to complete...

I left it running overnight for about 10 hours, but it never reached TEST PASSED.

From the host code, it looks like it is stuck at:

auto state = xrtRunWait(dmahls_rhdl);

In dma_hls.cpp, the possible blocking point seems to be:

s = strm_in.read();

So I suspect that dma_hls is waiting for data from the AIE/PL stream path and never receives enough output data.

My environment:

Vitis/Vivado: 2025.2.1
Tutorial branch: 2025.2
Platform: xilinx_vek280_base_202520_1
Common image: xilinx-versal-common-v2025.2
Target: hw_emu
LENET_INSTS: 1
ITER_CNT: 1

Connectivity in design/system_configs/lenet_x1.cfg:

stream_connect=dma_hls_0.strm_out:lenet_kernel_0.s_axis_ipr
stream_connect=lenet_kernel_0.m_axis_ipr:ai_engine_0.prod_in1
stream_connect=lenet_kernel_0.m_axis_m1r1:ai_engine_0.prod_in3
stream_connect=lenet_kernel_0.m_axis_m2r2_0:ai_engine_0.prod_in5
stream_connect=lenet_kernel_0.m_axis_m2r2_1:ai_engine_0.prod_in7

stream_connect=ai_engine_0.prod_out1:lenet_kernel_0.s_axis_m1r1
stream_connect=ai_engine_0.prod_out2:lenet_kernel_0.s_axis_m2r2
stream_connect=ai_engine_0.prod_out3:dma_hls_0.strm_in

Could you please advise what might cause the hardware emulation to hang at Waiting for dma hls to complete... even after setting MTMODEL=false?

Is there any additional environment variable, patch, or known workaround required for this tutorial in Vitis 2025.2 / 2025.2.1?

Thank you very much.