@@ -51,7 +51,6 @@ static const uint32_t hns_roce_opcode[] = {
5151 HR_IBV_OPC_MAP (RDMA_READ , RDMA_READ ),
5252 HR_IBV_OPC_MAP (ATOMIC_CMP_AND_SWP , ATOMIC_COM_AND_SWAP ),
5353 HR_IBV_OPC_MAP (ATOMIC_FETCH_AND_ADD , ATOMIC_FETCH_AND_ADD ),
54- HR_IBV_OPC_MAP (BIND_MW , BIND_MW_TYPE ),
5554 HR_IBV_OPC_MAP (SEND_WITH_INV , SEND_WITH_INV ),
5655};
5756
@@ -386,7 +385,6 @@ static const unsigned int wc_send_op_map[] = {
386385 [HNS_ROCE_SQ_OP_RDMA_READ ] = IBV_WC_RDMA_READ ,
387386 [HNS_ROCE_SQ_OP_ATOMIC_COMP_AND_SWAP ] = IBV_WC_COMP_SWAP ,
388387 [HNS_ROCE_SQ_OP_ATOMIC_FETCH_AND_ADD ] = IBV_WC_FETCH_ADD ,
389- [HNS_ROCE_SQ_OP_BIND_MW ] = IBV_WC_BIND_MW ,
390388};
391389
392390static const unsigned int wc_rcv_op_map [] = {
@@ -568,7 +566,6 @@ static void parse_cqe_for_req(struct hns_roce_v2_cqe *cqe, struct ibv_wc *wc,
568566 case HNS_ROCE_SQ_OP_SEND :
569567 case HNS_ROCE_SQ_OP_SEND_WITH_INV :
570568 case HNS_ROCE_SQ_OP_RDMA_WRITE :
571- case HNS_ROCE_SQ_OP_BIND_MW :
572569 wc -> wc_flags = 0 ;
573570 break ;
574571 case HNS_ROCE_SQ_OP_SEND_WITH_IMM :
@@ -1251,28 +1248,6 @@ static int set_rc_inl(struct hns_roce_qp *qp, const struct ibv_send_wr *wr,
12511248 return 0 ;
12521249}
12531250
1254- static void set_bind_mw_seg (struct hns_roce_rc_sq_wqe * wqe ,
1255- const struct ibv_send_wr * wr )
1256- {
1257- unsigned int access = wr -> bind_mw .bind_info .mw_access_flags ;
1258-
1259- hr_reg_write_bool (wqe , RCWQE_MW_TYPE , wr -> bind_mw .mw -> type - 1 );
1260- hr_reg_write_bool (wqe , RCWQE_MW_RA_EN ,
1261- !!(access & IBV_ACCESS_REMOTE_ATOMIC ));
1262- hr_reg_write_bool (wqe , RCWQE_MW_RR_EN ,
1263- !!(access & IBV_ACCESS_REMOTE_READ ));
1264- hr_reg_write_bool (wqe , RCWQE_MW_RW_EN ,
1265- !!(access & IBV_ACCESS_REMOTE_WRITE ));
1266-
1267- wqe -> new_rkey = htole32 (wr -> bind_mw .rkey );
1268- wqe -> byte_16 = htole32 (wr -> bind_mw .bind_info .length &
1269- HNS_ROCE_ADDRESS_MASK );
1270- wqe -> byte_20 = htole32 (wr -> bind_mw .bind_info .length >>
1271- HNS_ROCE_ADDRESS_SHIFT );
1272- wqe -> rkey = htole32 (wr -> bind_mw .bind_info .mr -> rkey );
1273- wqe -> va = htole64 (wr -> bind_mw .bind_info .addr );
1274- }
1275-
12761251static int check_rc_opcode (struct hns_roce_rc_sq_wqe * wqe ,
12771252 const struct ibv_send_wr * wr )
12781253{
@@ -1298,9 +1273,6 @@ static int check_rc_opcode(struct hns_roce_rc_sq_wqe *wqe,
12981273 case IBV_WR_SEND_WITH_INV :
12991274 wqe -> inv_key = htole32 (wr -> invalidate_rkey );
13001275 break ;
1301- case IBV_WR_BIND_MW :
1302- set_bind_mw_seg (wqe , wr );
1303- break ;
13041276 default :
13051277 ret = EINVAL ;
13061278 break ;
@@ -1334,9 +1306,6 @@ static int set_rc_wqe(void *wqe, struct hns_roce_qp *qp, struct ibv_send_wr *wr,
13341306 hr_reg_write (rc_sq_wqe , RCWQE_MSG_START_SGE_IDX ,
13351307 sge_info -> start_idx & (qp -> ex_sge .sge_cnt - 1 ));
13361308
1337- if (wr -> opcode == IBV_WR_BIND_MW )
1338- goto wqe_valid ;
1339-
13401309 wqe += sizeof (struct hns_roce_rc_sq_wqe );
13411310 dseg = wqe ;
13421311
@@ -1357,7 +1326,6 @@ static int set_rc_wqe(void *wqe, struct hns_roce_qp *qp, struct ibv_send_wr *wr,
13571326 if (ret )
13581327 return ret ;
13591328
1360- wqe_valid :
13611329 enable_wqe (qp , rc_sq_wqe , qp -> sq .head + nreq );
13621330
13631331 return 0 ;
0 commit comments