Add OSS CI to cross-compile and run the Cadence Xtensa backend (#20208)#20208
Add OSS CI to cross-compile and run the Cadence Xtensa backend (#20208)#20208aliafzal wants to merge 1 commit into
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🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/20208
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@aliafzal has imported this pull request. If you are a Meta employee, you can view this in D108258574. |
Summary: Adds OSS CI to cross-compile and run the Cadence (Xtensa) backend, so backend changes can be validated in CI rather than only through internal flows. - **gflags-free ISS runner** (`cadence_executor_runner`): the upstream `executor_runner` can't cross-compile to Xtensa (gflags pulls in `mkdir(2)`, absent from Xtensa newlib). This uses argv-only parsing like the Arm/NXP backends, loads a `.pte`, and runs the first method on the simulator. Also registers the `quantized_depthwise_conv1d` ops the HiFi4 codegen references but the operators CMake omitted (broke the link). - **`xtensa-build` job** added to the existing Cadence Build & Test workflow (`build-cadence-runner.yml`), alongside the host `cpu-build`/`cpu-test`. It cross-compiles the runner for the `hifi4` and `vision` cores and uploads it; an ISS test stage follows later (cf. `cpu-build` -> `cpu-test`). The licensed toolchain/core artifacts are fetched at runtime from an auth-gated store via a short-lived OIDC credential; role/region/store are supplied via CI variables and are not committed. Test Plan: Validated locally end to end: setup + cross-compile produce an Xtensa ELF runner for `vision`; the HiFi4 op sweep passes 15/15 on the simulator and a trivial model returns the expected output. Differential Revision: D108258574 Pulled By: aliafzal
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@aliafzal has exported this pull request. If you are a Meta employee, you can view the originating Diff in D108258574. |
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@claude review this PR |
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Claude finished @rascani's task in 4m 13s —— View job PR Review: Add OSS CI for Cadence Xtensa backend
Nice, well-documented change — the inline comments explaining why (gflags→ Workflow / CI1. hifi-build:
if: github.repository_owner == 'pytorch'Otherwise the red X on fork PRs will be noise. Fix this → 2. CodeQL: no top-level permissions: {}near the top (after
C++ runner (
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This largely looks good to me. Claude had some good feedback, but I'd also add on that we may want to consider starting this workflow on nightly or trunk and then moving it up to pull once it proves stable. |
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Forgot to add - Thank you so much for putting this together @aliafzal. I'm really excited about having this in OSS. |
huydhn
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The CI looks good to me! I leave the rest of the PR for the team to review
| build: | ||
| name: ${{ inputs.backend }} | ||
| runs-on: linux.2xlarge | ||
| environment: cadence |
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Just to note that being able to access to this environment means being able to access the S3 bucket. The access can be granted in several ways:
- Explicit approvals
- Branches, only allow certain branches like main to run the job
Summary:
Adds OSS CI to cross-compile and run the Cadence (Xtensa) backend, so backend changes can be validated in CI rather than only through internal flows.
cadence_executor_runner): the upstreamexecutor_runnercan't cross-compile to Xtensa (gflags pulls inmkdir(2), absent from Xtensa newlib). This uses argv-only parsing like the Arm/NXP backends, loads a.pte, and runs the first method on the simulator. Also registers thequantized_depthwise_conv1dops the HiFi4 codegen references but the operators CMake omitted (broke the link).xtensa-buildjob added to the existing Cadence Build & Test workflow (build-cadence-runner.yml), alongside the hostcpu-build/cpu-test. It cross-compiles the runner for thehifi4andvisioncores and uploads it; an ISS test stage follows later (cf.cpu-build->cpu-test). The licensed toolchain/core artifacts are fetched at runtime from an auth-gated store via a short-lived OIDC credential; role/region/store are supplied via CI variables and are not committed.Test Plan: Validated locally end to end: setup + cross-compile produce an Xtensa ELF runner for
vision; the HiFi4 op sweep passes 15/15 on the simulator and a trivial model returns the expected output.Differential Revision: D108258574
Pulled By: aliafzal