diff --git a/README.md b/README.md index be9d2a00f..782fbc99f 100644 --- a/README.md +++ b/README.md @@ -186,13 +186,16 @@ just use search and replace, manual changes are required pretty infrequently. For best performance, in addition to `-O3` (or whatever your compiler's -equivalent is), you should enable OpenMP 4 SIMD support by defining -`SIMDE_ENABLE_OPENMP` before including any SIMDe headers, and -enabling OpenMP support in your compiler. GCC and ICC both support a -flag to enable only OpenMP SIMD support instead of full OpenMP (the OpenMP -SIMD support doesn't require the OpenMP run-time library); for GCC the -flag is `-fopenmp-simd` (requires GCC version 4.9 or later), for ICC -the flag is `-qopenmp-simd`. SIMDe also supports +equivalent is), you should enable OpenMP 4 SIMD support in your compiler. +GCC and ICC both support a flag to enable only OpenMP SIMD support instead +of full OpenMP (the OpenMP SIMD support doesn't require the OpenMP run-time +library); for GCC the flag is `-fopenmp-simd` (requires GCC version 4.9 +or later), for ICC the flag is `-qopenmp-simd`. Some compilers have this +support implicitly enabled (the example is MCST Elbrus Compiler, or LCC +for short). If for some reason you need to disable OpenMP support, +you need to define `SIMDE_DISABLE_OPENMP` before including any of SIMDe +headers, and probably disable its support in compiler, if it is implicitly +enabled (for LCC, there is `-fno-openmp` flag). SIMDe also supports using [Cilk Plus](https://www.cilkplus.org/), [GCC loop-specific pragmas](https://gcc.gnu.org/onlinedocs/gcc/Loop-Specific-Pragmas.html), or [clang pragma loop hint diff --git a/meson.build b/meson.build index 897d95498..7aa549a10 100644 --- a/meson.build +++ b/meson.build @@ -8,15 +8,6 @@ project('SIMDe', 'c', 'cpp', cc = meson.get_compiler('c') cxx = meson.get_compiler('cpp') -foreach additional_arg : [ '-Wno-reduced-alignment' ] - if cc.has_argument(additional_arg) - add_global_arguments(additional_arg, language : 'c') - endif - if cxx.has_argument(additional_arg) - add_global_arguments(additional_arg, language : 'cpp') - endif -endforeach - simde_neon_families = [ 'aba', 'abd', diff --git a/simde/arm/neon/types.h b/simde/arm/neon/types.h index 0ce4bf1da..e84aaed2e 100644 --- a/simde/arm/neon/types.h +++ b/simde/arm/neon/types.h @@ -174,7 +174,7 @@ SIMDE_ARM_NEON_TYPE_FLOAT_DEFINE_(64, 2, SIMDE_ALIGN_16_) #define SIMDE_ARM_NEON_NEED_PORTABLE_F64X1XN #define SIMDE_ARM_NEON_NEED_PORTABLE_F64X2XN #endif -#elif defined(SIMDE_ARCH_X86) || defined(SIMDE_ARCH_AMD64) +#elif defined(SIMDE_ARCH_X86) || defined(SIMDE_ARCH_AMD64) || defined(SIMDE_ARCH_E2K) #define SIMDE_ARM_NEON_NEED_PORTABLE_F32 #define SIMDE_ARM_NEON_NEED_PORTABLE_F64 diff --git a/simde/simde-align.h b/simde/simde-align.h index e35ef5980..8a71dc8dc 100644 --- a/simde/simde-align.h +++ b/simde/simde-align.h @@ -116,6 +116,7 @@ #define SIMDE_ALIGN_OF(Type) alignof(Type) #elif \ HEDLEY_GCC_VERSION_CHECK(2,95,0) || \ + HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) || \ HEDLEY_ARM_VERSION_CHECK(4,1,0) || \ HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ HEDLEY_SUNPRO_VERSION_CHECK(5,13,0) || \ @@ -264,6 +265,7 @@ #if \ HEDLEY_HAS_ATTRIBUTE(aligned) || \ HEDLEY_GCC_VERSION_CHECK(2,95,0) || \ + HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) || \ HEDLEY_CRAY_VERSION_CHECK(8,4,0) || \ HEDLEY_IBM_VERSION_CHECK(11,1,0) || \ HEDLEY_INTEL_VERSION_CHECK(13,0,0) || \ @@ -314,7 +316,8 @@ */ #if \ HEDLEY_HAS_BUILTIN(__builtin_assume_aligned) || \ - HEDLEY_GCC_VERSION_CHECK(4,7,0) + HEDLEY_GCC_VERSION_CHECK(4,7,0) || \ + HEDLEY_MCST_LCC_VERSION_CHECK(1,25,10) #define SIMDE_ALIGN_ASSUME_TO_UNCHECKED(Pointer, Alignment) \ HEDLEY_REINTERPRET_CAST(__typeof__(Pointer), __builtin_assume_aligned(HEDLEY_CONST_CAST(void*, HEDLEY_REINTERPRET_CAST(const void*, Pointer)), Alignment)) #elif HEDLEY_INTEL_VERSION_CHECK(13,0,0) @@ -446,4 +449,18 @@ */ #define SIMDE_ALIGN_ASSUME_CAST(Type, Pointer) SIMDE_ALIGN_ASSUME_LIKE(SIMDE_ALIGN_CAST(Type, Pointer), Type) +/* In some circumstances we need to define types as packed, + * because platform alignment is fixed when variable is placed + * on the stack (but this alignment is variable otherwise). + * so there's SIMDE_ALIGN_REDUCE_STRUCT macros that allows this + * for LCC compiler on Elbrus architecture. + */ +#if defined (SIMDE_BUG_LCC_STACK_ALIGNMENT_CAP) + #define SIMDE_ALIGN_REDUCE_STRUCT __attribute__((packed, aligned(16))) + #define SIMDE_ALIGN_REDUCE_ARRAY __attribute__((aligned(16))) +#else + #define SIMDE_ALIGN_REDUCE_STRUCT + #define SIMDE_ALIGN_REDUCE_ARRAY +#endif + #endif /* !defined(SIMDE_ALIGN_H) */ diff --git a/simde/simde-arch.h b/simde/simde-arch.h index 731e677e6..287bf1722 100644 --- a/simde/simde-arch.h +++ b/simde/simde-arch.h @@ -182,13 +182,28 @@ */ #if defined(__e2k__) #define SIMDE_ARCH_E2K -#define SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS /* Discard features unsupported by compiler */ #endif /* Discard features unsupported by Elbrus compiler. For lcc > 1.25.10, it may be based on a version. */ #if defined(__LCC__) -#define SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS +#define SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES +#define SIMDE_BUG_LCC_XOP_MISSING +#define SIMDE_BUG_LCC_WARNING_ON_SHIFTS +#define SIMDE_BUG_LCC_FMA_WRONG_RESULT +#define SIMDE_BUG_LCC_AVX_NO_LOAD_STORE_U2 +#define SIMDE_BUG_LCC_STACK_ALIGNMENT_CAP + +/* Some native functions on E2K with instruction set < v6 + are declared as deprecated due to inefficiency. + Still they are more efficient than SIMDe implementation. + So we're using them, and switching off these deprecation warnings. */ +#define SIMDE_BUG_PCLMUL_XOP_DEPRECATED +#define SIMDE_LCC_DISABLE_DEPRECATED_WARNINGS _Pragma("diag_suppress 1215,1444") +#define SIMDE_LCC_REVERT_DEPRECATED_WARNINGS _Pragma("diag_default 1215,1444") +#else +#define SIMDE_LCC_DISABLE_DEPRECATED_WARNINGS +#define SIMDE_LCC_REVERT_DEPRECATED_WARNINGS #endif /* HP/PA / PA-RISC @@ -267,7 +282,7 @@ # if defined(__SSE4_2__) # define SIMDE_ARCH_X86_SSE4_2 1 # endif -# if defined(__XOP__) && !defined(__LCC__) /* LCC incorrectly defines __XOP__ */ +# if defined(__XOP__) # define SIMDE_ARCH_X86_XOP 1 # endif # if defined(__AVX__) @@ -285,7 +300,7 @@ # if defined(__AVX2__) # define SIMDE_ARCH_X86_AVX2 1 # endif -# if defined(__FMA__) && !defined(__LCC__) /* LCC incorrectly defines __FMA__ */ +# if defined(__FMA__) # define SIMDE_ARCH_X86_FMA 1 # if !defined(SIMDE_ARCH_X86_AVX) # define SIMDE_ARCH_X86_AVX 1 @@ -315,7 +330,7 @@ # if defined(__GFNI__) # define SIMDE_ARCH_X86_GFNI 1 # endif -# if defined(__PCLMUL__) && !defined(SIMDE_ARCH_E2K) /* E2K has inefficient implementation of PCLMUL */ +# if defined(__PCLMUL__) # define SIMDE_ARCH_X86_PCLMUL 1 # endif # if defined(__VPCLMULQDQ__) diff --git a/simde/simde-common.h b/simde/simde-common.h index 35b0e86e3..a80b44351 100644 --- a/simde/simde-common.h +++ b/simde/simde-common.h @@ -291,8 +291,14 @@ # endif #endif -#if !defined(SIMDE_ENABLE_OPENMP) && ((defined(_OPENMP) && (_OPENMP >= 201307L)) || (defined(_OPENMP_SIMD) && (_OPENMP_SIMD >= 201307L))) -# define SIMDE_ENABLE_OPENMP +#if !defined(SIMDE_DISABLE_OPENMP) + #if !defined(SIMDE_ENABLE_OPENMP) && ((defined(_OPENMP) && (_OPENMP >= 201307L)) || (defined(_OPENMP_SIMD) && (_OPENMP_SIMD >= 201307L))) + # define SIMDE_ENABLE_OPENMP + #endif +#else + #if defined(SIMDE_ENABLE_OPENMP) + # undef SIMDE_ENABLE_OPENMP + #endif #endif #if !defined(SIMDE_ENABLE_CILKPLUS) && (defined(__cilk) || defined(HEDLEY_INTEL_VERSION)) @@ -322,7 +328,7 @@ # define SIMDE_VECTORIZE_SAFELEN(l) HEDLEY_PRAGMA(clang loop vectorize_width(l)) # define SIMDE_VECTORIZE_REDUCTION(r) SIMDE_VECTORIZE # define SIMDE_VECTORIZE_ALIGNED(a) -#elif HEDLEY_GCC_VERSION_CHECK(4,9,0) && !defined(__LCC__) +#elif HEDLEY_GCC_VERSION_CHECK(4,9,0) # define SIMDE_VECTORIZE HEDLEY_PRAGMA(GCC ivdep) # define SIMDE_VECTORIZE_SAFELEN(l) SIMDE_VECTORIZE # define SIMDE_VECTORIZE_REDUCTION(r) SIMDE_VECTORIZE diff --git a/simde/x86/avx.h b/simde/x86/avx.h index bb03f795c..f526b1133 100644 --- a/simde/x86/avx.h +++ b/simde/x86/avx.h @@ -91,7 +91,7 @@ typedef union { SIMDE_ALIGN_TO_16 SIMDE_POWER_ALTIVEC_VECTOR(double) altivec_f64[2]; #endif #endif -} simde__m256_private; +} SIMDE_ALIGN_REDUCE_STRUCT simde__m256_private; typedef union { #if defined(SIMDE_VECTOR_SUBSCRIPT) @@ -149,7 +149,7 @@ typedef union { SIMDE_ALIGN_TO_16 SIMDE_POWER_ALTIVEC_VECTOR(double) altivec_f64[2]; #endif #endif -} simde__m256d_private; +} SIMDE_ALIGN_REDUCE_STRUCT simde__m256d_private; typedef union { #if defined(SIMDE_VECTOR_SUBSCRIPT) @@ -207,7 +207,7 @@ typedef union { SIMDE_ALIGN_TO_16 SIMDE_POWER_ALTIVEC_VECTOR(double) altivec_f64[2]; #endif #endif -} simde__m256i_private; +} SIMDE_ALIGN_REDUCE_STRUCT simde__m256i_private; #if defined(SIMDE_X86_AVX_NATIVE) typedef __m256 simde__m256; @@ -3935,7 +3935,7 @@ simde_mm256_loadu_si256 (void const * mem_addr) { SIMDE_FUNCTION_ATTRIBUTES simde__m256 simde_mm256_loadu2_m128 (const float hiaddr[HEDLEY_ARRAY_PARAM(4)], const float loaddr[HEDLEY_ARRAY_PARAM(4)]) { - #if defined(SIMDE_X86_AVX_NATIVE) && !defined(SIMDE_BUG_GCC_91341) + #if defined(SIMDE_X86_AVX_NATIVE) && !defined(SIMDE_BUG_GCC_91341) && !defined(SIMDE_BUG_LCC_AVX_NO_LOAD_STORE_U2) return _mm256_loadu2_m128(hiaddr, loaddr); #else return @@ -3951,7 +3951,7 @@ simde_mm256_loadu2_m128 (const float hiaddr[HEDLEY_ARRAY_PARAM(4)], const float SIMDE_FUNCTION_ATTRIBUTES simde__m256d simde_mm256_loadu2_m128d (const double hiaddr[HEDLEY_ARRAY_PARAM(2)], const double loaddr[HEDLEY_ARRAY_PARAM(2)]) { - #if defined(SIMDE_X86_AVX_NATIVE) && !defined(SIMDE_BUG_GCC_91341) + #if defined(SIMDE_X86_AVX_NATIVE) && !defined(SIMDE_BUG_GCC_91341) && !defined(SIMDE_BUG_LCC_AVX_NO_LOAD_STORE_U2) return _mm256_loadu2_m128d(hiaddr, loaddr); #else return @@ -3967,7 +3967,7 @@ simde_mm256_loadu2_m128d (const double hiaddr[HEDLEY_ARRAY_PARAM(2)], const doub SIMDE_FUNCTION_ATTRIBUTES simde__m256i simde_mm256_loadu2_m128i (const simde__m128i* hiaddr, const simde__m128i* loaddr) { - #if defined(SIMDE_X86_AVX_NATIVE) && !defined(SIMDE_BUG_GCC_91341) + #if defined(SIMDE_X86_AVX_NATIVE) && !defined(SIMDE_BUG_GCC_91341) && !defined(SIMDE_BUG_LCC_AVX_NO_LOAD_STORE_U2) return _mm256_loadu2_m128i(hiaddr, loaddr); #else return @@ -4547,8 +4547,21 @@ simde_mm256_permute_ps (simde__m256 a, const int imm8) return simde__m256_from_private(r_); } #if defined(SIMDE_X86_AVX_NATIVE) +#if defined(SIMDE_BUG_LCC_STACK_ALIGNMENT_CAP) +/* Patched implementation from e2kbuiltin.h */ +# define simde_mm256_permute_ps(a, imm8) ({ \ + type_union_256 __attribute__((aligned(16))) __s, __dst; \ + __s.__v8sf = (__v8sf)(a); \ + SELECT_CONST_32F (__s.l.l1, __s.l.l0, __dst.l.l0, (imm8)); \ + SELECT_CONST_32F (__s.l.l1, __s.l.l0, __dst.l.l1, (imm8) >> 4); \ + SELECT_CONST_32F (__s.l.l3, __s.l.l2, __dst.l.l2, (imm8)); \ + SELECT_CONST_32F (__s.l.l3, __s.l.l2, __dst.l.l3, (imm8) >> 4); \ + (__m256)(__dst.__v8sf); \ +}) +#else # define simde_mm256_permute_ps(a, imm8) _mm256_permute_ps(a, imm8) #endif +#endif #if defined(SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES) #undef _mm256_permute_ps #define _mm256_permute_ps(a, imm8) simde_mm256_permute_ps(a, imm8) @@ -5023,9 +5036,9 @@ simde_mm256_shuffle_ps (simde__m256 a, simde__m256 b, const int imm8) return simde__m256_from_private(r_); } -#if defined(SIMDE_X86_AVX_NATIVE) +#if defined(SIMDE_X86_AVX_NATIVE) && !defined(SIMDE_BUG_LCC_STACK_ALIGNMENT_CAP) #define simde_mm256_shuffle_ps(a, b, imm8) _mm256_shuffle_ps(a, b, imm8) -#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) +#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) || defined(SIMDE_BUG_LCC_STACK_ALIGNMENT_CAP) #define simde_mm256_shuffle_ps(a, b, imm8) \ simde_mm256_set_m128( \ simde_mm_shuffle_ps(simde_mm256_extractf128_ps(a, 1), simde_mm256_extractf128_ps(b, 1), (imm8)), \ @@ -5230,7 +5243,7 @@ simde_mm256_storeu_si256 (void* mem_addr, simde__m256i a) { SIMDE_FUNCTION_ATTRIBUTES void simde_mm256_storeu2_m128 (simde_float32 hi_addr[4], simde_float32 lo_addr[4], simde__m256 a) { - #if defined(SIMDE_X86_AVX_NATIVE) && !defined(SIMDE_BUG_GCC_91341) + #if defined(SIMDE_X86_AVX_NATIVE) && !defined(SIMDE_BUG_GCC_91341) && !defined(SIMDE_BUG_LCC_AVX_NO_LOAD_STORE_U2) _mm256_storeu2_m128(hi_addr, lo_addr, a); #else simde_mm_storeu_ps(lo_addr, simde_mm256_castps256_ps128(a)); @@ -5245,7 +5258,7 @@ simde_mm256_storeu2_m128 (simde_float32 hi_addr[4], simde_float32 lo_addr[4], si SIMDE_FUNCTION_ATTRIBUTES void simde_mm256_storeu2_m128d (simde_float64 hi_addr[2], simde_float64 lo_addr[2], simde__m256d a) { - #if defined(SIMDE_X86_AVX_NATIVE) && !defined(SIMDE_BUG_GCC_91341) + #if defined(SIMDE_X86_AVX_NATIVE) && !defined(SIMDE_BUG_GCC_91341) && !defined(SIMDE_BUG_LCC_AVX_NO_LOAD_STORE_U2) _mm256_storeu2_m128d(hi_addr, lo_addr, a); #else simde_mm_storeu_pd(lo_addr, simde_mm256_castpd256_pd128(a)); @@ -5260,7 +5273,7 @@ simde_mm256_storeu2_m128d (simde_float64 hi_addr[2], simde_float64 lo_addr[2], s SIMDE_FUNCTION_ATTRIBUTES void simde_mm256_storeu2_m128i (simde__m128i* hi_addr, simde__m128i* lo_addr, simde__m256i a) { - #if defined(SIMDE_X86_AVX_NATIVE) && !defined(SIMDE_BUG_GCC_91341) + #if defined(SIMDE_X86_AVX_NATIVE) && !defined(SIMDE_BUG_GCC_91341) && !defined(SIMDE_BUG_LCC_AVX_NO_LOAD_STORE_U2) _mm256_storeu2_m128i(hi_addr, lo_addr, a); #else simde_mm_storeu_si128(lo_addr, simde_mm256_castsi256_si128(a)); diff --git a/simde/x86/avx2.h b/simde/x86/avx2.h index e2fe7cf8e..581159a55 100644 --- a/simde/x86/avx2.h +++ b/simde/x86/avx2.h @@ -300,9 +300,9 @@ simde_mm256_alignr_epi8 (simde__m256i a, simde__m256i b, int count) return simde__m256i_from_private(r_); } -#if defined(SIMDE_X86_AVX2_NATIVE) +#if defined(SIMDE_X86_AVX2_NATIVE) && !defined(SIMDE_BUG_LCC_STACK_ALIGNMENT_CAP) # define simde_mm256_alignr_epi8(a, b, count) _mm256_alignr_epi8(a, b, count) -#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) +#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) || defined(SIMDE_BUG_LCC_STACK_ALIGNMENT_CAP) # define simde_mm256_alignr_epi8(a, b, count) \ simde_mm256_set_m128i( \ simde_mm_alignr_epi8(simde_mm256_extracti128_si256(a, 1), simde_mm256_extracti128_si256(b, 1), (count)), \ @@ -596,9 +596,9 @@ simde_mm256_blend_epi16(simde__m256i a, simde__m256i b, const int imm8) } #if defined(SIMDE_X86_AVX2_NATIVE) && defined(SIMDE_BUG_CLANG_REV_234560) # define simde_mm256_blend_epi16(a, b, imm8) _mm256_castpd_si256(_mm256_blend_epi16(a, b, imm8)) -#elif defined(SIMDE_X86_AVX2_NATIVE) +#elif defined(SIMDE_X86_AVX2_NATIVE) && !defined(SIMDE_BUG_LCC_STACK_ALIGNMENT_CAP) # define simde_mm256_blend_epi16(a, b, imm8) _mm256_blend_epi16(a, b, imm8) -#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) +#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) || defined(SIMDE_BUG_LCC_STACK_ALIGNMENT_CAP) # define simde_mm256_blend_epi16(a, b, imm8) \ simde_mm256_set_m128i( \ simde_mm_blend_epi16(simde_mm256_extracti128_si256(a, 1), simde_mm256_extracti128_si256(b, 1), (imm8)), \ @@ -1166,7 +1166,7 @@ simde_mm256_cmpgt_epi8 (simde__m256i a, simde__m256i b) { #if SIMDE_NATURAL_VECTOR_SIZE_LE(128) r_.m128i[0] = simde_mm_cmpgt_epi8(a_.m128i[0], b_.m128i[0]); r_.m128i[1] = simde_mm_cmpgt_epi8(a_.m128i[1], b_.m128i[1]); - #elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.i8 = HEDLEY_STATIC_CAST(__typeof__(r_.i8), a_.i8 > b_.i8); #else SIMDE_VECTORIZE @@ -3934,9 +3934,9 @@ simde_mm256_shuffle_epi32 (simde__m256i a, const int imm8) return simde__m256i_from_private(r_); } -#if defined(SIMDE_X86_AVX2_NATIVE) +#if defined(SIMDE_X86_AVX2_NATIVE) && !defined(SIMDE_BUG_LCC_STACK_ALIGNMENT_CAP) # define simde_mm256_shuffle_epi32(a, imm8) _mm256_shuffle_epi32(a, imm8) -#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) && !defined(__PGI) +#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) && !defined(__PGI) || defined(SIMDE_BUG_LCC_STACK_ALIGNMENT_CAP) # define simde_mm256_shuffle_epi32(a, imm8) \ simde_mm256_set_m128i( \ simde_mm_shuffle_epi32(simde_mm256_extracti128_si256(a, 1), (imm8)), \ @@ -3962,9 +3962,9 @@ simde_mm256_shuffle_epi32 (simde__m256i a, const int imm8) #define _mm256_shuffle_epi32(a, imm8) simde_mm256_shuffle_epi32(a, imm8) #endif -#if defined(SIMDE_X86_AVX2_NATIVE) +#if defined(SIMDE_X86_AVX2_NATIVE) && !defined(SIMDE_BUG_LCC_STACK_ALIGNMENT_CAP) # define simde_mm256_shufflehi_epi16(a, imm8) _mm256_shufflehi_epi16(a, imm8) -#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) +#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) || defined(SIMDE_BUG_LCC_STACK_ALIGNMENT_CAP) # define simde_mm256_shufflehi_epi16(a, imm8) \ simde_mm256_set_m128i( \ simde_mm_shufflehi_epi16(simde_mm256_extracti128_si256(a, 1), (imm8)), \ @@ -3998,9 +3998,9 @@ simde_mm256_shuffle_epi32 (simde__m256i a, const int imm8) #define _mm256_shufflehi_epi16(a, imm8) simde_mm256_shufflehi_epi16(a, imm8) #endif -#if defined(SIMDE_X86_AVX2_NATIVE) +#if defined(SIMDE_X86_AVX2_NATIVE) && !defined(SIMDE_BUG_LCC_STACK_ALIGNMENT_CAP) # define simde_mm256_shufflelo_epi16(a, imm8) _mm256_shufflelo_epi16(a, imm8) -#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) +#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) || defined(SIMDE_BUG_LCC_STACK_ALIGNMENT_CAP) # define simde_mm256_shufflelo_epi16(a, imm8) \ simde_mm256_set_m128i( \ simde_mm_shufflelo_epi16(simde_mm256_extracti128_si256(a, 1), (imm8)), \ @@ -4350,9 +4350,9 @@ simde_mm256_slli_si256 (simde__m256i a, const int imm8) return simde__m256i_from_private(r_); } -#if defined(SIMDE_X86_AVX2_NATIVE) +#if defined(SIMDE_X86_AVX2_NATIVE) && !defined(SIMDE_BUG_LCC_STACK_ALIGNMENT_CAP) # define simde_mm256_slli_si256(a, imm8) _mm256_slli_si256(a, imm8) -#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) && !defined(__PGI) +#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) && !defined(__PGI) || defined(SIMDE_BUG_LCC_STACK_ALIGNMENT_CAP) # define simde_mm256_slli_si256(a, imm8) \ simde_mm256_set_m128i( \ simde_mm_slli_si128(simde_mm256_extracti128_si256(a, 1), (imm8)), \ @@ -4379,7 +4379,7 @@ simde_mm_sllv_epi32 (simde__m128i a, simde__m128i b) { #if defined(SIMDE_ARM_NEON_A32V7_NATIVE) r_.neon_u32 = vshlq_u32(a_.neon_u32, vreinterpretq_s32_u32(b_.neon_u32)); r_.neon_u32 = vandq_u32(r_.neon_u32, vcltq_u32(b_.neon_u32, vdupq_n_u32(32))); - #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.u32 = HEDLEY_STATIC_CAST(__typeof__(r_.u32), (b_.u32 < 32) & (a_.u32 << b_.u32)); #else SIMDE_VECTORIZE @@ -4409,7 +4409,7 @@ simde_mm256_sllv_epi32 (simde__m256i a, simde__m256i b) { #if SIMDE_NATURAL_VECTOR_SIZE_LE(128) r_.m128i[0] = simde_mm_sllv_epi32(a_.m128i[0], b_.m128i[0]); r_.m128i[1] = simde_mm_sllv_epi32(a_.m128i[1], b_.m128i[1]); - #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.u32 = HEDLEY_STATIC_CAST(__typeof__(r_.u32), (b_.u32 < 32) & (a_.u32 << b_.u32)); #else SIMDE_VECTORIZE @@ -4439,7 +4439,7 @@ simde_mm_sllv_epi64 (simde__m128i a, simde__m128i b) { #if defined(SIMDE_ARM_NEON_A64V8_NATIVE) r_.neon_u64 = vshlq_u64(a_.neon_u64, vreinterpretq_s64_u64(b_.neon_u64)); r_.neon_u64 = vandq_u64(r_.neon_u64, vcltq_u64(b_.neon_u64, vdupq_n_u64(64))); - #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.u64 = HEDLEY_STATIC_CAST(__typeof__(r_.u64), (b_.u64 < 64) & (a_.u64 << b_.u64)); #else SIMDE_VECTORIZE @@ -4469,7 +4469,7 @@ simde_mm256_sllv_epi64 (simde__m256i a, simde__m256i b) { #if SIMDE_NATURAL_VECTOR_SIZE_LE(128) r_.m128i[0] = simde_mm_sllv_epi64(a_.m128i[0], b_.m128i[0]); r_.m128i[1] = simde_mm_sllv_epi64(a_.m128i[1], b_.m128i[1]); - #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.u64 = HEDLEY_STATIC_CAST(__typeof__(r_.u64), (b_.u64 < 64) & (a_.u64 << b_.u64)); #else SIMDE_VECTORIZE @@ -4940,9 +4940,9 @@ simde_mm256_srli_si256 (simde__m256i a, const int imm8) return simde__m256i_from_private(r_); } -#if defined(SIMDE_X86_AVX2_NATIVE) +#if defined(SIMDE_X86_AVX2_NATIVE) && !defined(SIMDE_BUG_LCC_STACK_ALIGNMENT_CAP) # define simde_mm256_srli_si256(a, imm8) _mm256_srli_si256(a, imm8) -#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) && !defined(__PGI) +#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) && !defined(__PGI) || defined(SIMDE_BUG_LCC_STACK_ALIGNMENT_CAP) # define simde_mm256_srli_si256(a, imm8) \ simde_mm256_set_m128i( \ simde_mm_srli_si128(simde_mm256_extracti128_si256(a, 1), (imm8)), \ @@ -4966,7 +4966,7 @@ simde_mm_srlv_epi32 (simde__m128i a, simde__m128i b) { b_ = simde__m128i_to_private(b), r_; - #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.u32 = HEDLEY_STATIC_CAST(__typeof__(r_.u32), (b_.u32 < 32) & (a_.u32 >> b_.u32)); #else SIMDE_VECTORIZE @@ -4993,7 +4993,7 @@ simde_mm256_srlv_epi32 (simde__m256i a, simde__m256i b) { b_ = simde__m256i_to_private(b), r_; - #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.u32 = HEDLEY_STATIC_CAST(__typeof__(r_.u32), (b_.u32 < 32) & (a_.u32 >> b_.u32)); #else SIMDE_VECTORIZE @@ -5020,7 +5020,7 @@ simde_mm_srlv_epi64 (simde__m128i a, simde__m128i b) { b_ = simde__m128i_to_private(b), r_; - #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.u64 = HEDLEY_STATIC_CAST(__typeof__(r_.u64), (b_.u64 < 64) & (a_.u64 >> b_.u64)); #else SIMDE_VECTORIZE @@ -5047,7 +5047,7 @@ simde_mm256_srlv_epi64 (simde__m256i a, simde__m256i b) { b_ = simde__m256i_to_private(b), r_; - #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.u64 = HEDLEY_STATIC_CAST(__typeof__(r_.u64), (b_.u64 < 64) & (a_.u64 >> b_.u64)); #else SIMDE_VECTORIZE diff --git a/simde/x86/avx512/cmpeq.h b/simde/x86/avx512/cmpeq.h index b20859e13..1c8c20ef8 100644 --- a/simde/x86/avx512/cmpeq.h +++ b/simde/x86/avx512/cmpeq.h @@ -57,7 +57,7 @@ simde_mm512_cmpeq_epi8_mask (simde__m512i a, simde__m512i b) { const uint32_t t = HEDLEY_STATIC_CAST(uint32_t, simde_mm256_movemask_epi8(simde_mm256_cmpeq_epi8(a_.m256i[i], b_.m256i[i]))); r |= HEDLEY_STATIC_CAST(uint64_t, t) << (i * 32); } - #elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) simde__m512i_private tmp; tmp.i8 = HEDLEY_STATIC_CAST(__typeof__(tmp.i8), a_.i8 == b_.i8); diff --git a/simde/x86/avx512/cmpge.h b/simde/x86/avx512/cmpge.h index 8d8cf33ff..4dd6df8f4 100644 --- a/simde/x86/avx512/cmpge.h +++ b/simde/x86/avx512/cmpge.h @@ -47,7 +47,7 @@ simde_mm512_cmpge_epi8_mask (simde__m512i a, simde__m512i b) { b_ = simde__m512i_to_private(b); simde__mmask64 r = 0; - #if defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #if defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) simde__m512i_private tmp; tmp.i8 = HEDLEY_STATIC_CAST(__typeof__(tmp.i8), a_.i8 >= b_.i8); @@ -78,7 +78,7 @@ simde_mm512_cmpge_epu8_mask (simde__m512i a, simde__m512i b) { b_ = simde__m512i_to_private(b); simde__mmask64 r = 0; - #if defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #if defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) simde__m512i_private tmp; tmp.i8 = HEDLEY_STATIC_CAST(__typeof__(tmp.i8), a_.u8 >= b_.u8); diff --git a/simde/x86/avx512/cmpgt.h b/simde/x86/avx512/cmpgt.h index 3e299b531..d9017b53c 100644 --- a/simde/x86/avx512/cmpgt.h +++ b/simde/x86/avx512/cmpgt.h @@ -56,7 +56,7 @@ simde_mm512_cmpgt_epi8_mask (simde__m512i a, simde__m512i b) { const uint32_t t = HEDLEY_STATIC_CAST(uint32_t, simde_mm256_movemask_epi8(simde_mm256_cmpgt_epi8(a_.m256i[i], b_.m256i[i]))); r |= HEDLEY_STATIC_CAST(uint64_t, t) << HEDLEY_STATIC_CAST(uint64_t, i * 32); } - #elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) simde__m512i_private tmp; tmp.i8 = HEDLEY_STATIC_CAST(__typeof__(tmp.i8), a_.i8 > b_.i8); @@ -89,7 +89,7 @@ simde_mm512_cmpgt_epu8_mask (simde__m512i a, simde__m512i b) { b_ = simde__m512i_to_private(b); simde__mmask64 r = 0; - #if defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #if defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) simde__m512i_private tmp; tmp.i8 = HEDLEY_STATIC_CAST(__typeof__(tmp.i8), a_.u8 > b_.u8); diff --git a/simde/x86/avx512/cmple.h b/simde/x86/avx512/cmple.h index 04befa913..a8152be02 100644 --- a/simde/x86/avx512/cmple.h +++ b/simde/x86/avx512/cmple.h @@ -46,7 +46,7 @@ simde_mm512_cmple_epi8_mask (simde__m512i a, simde__m512i b) { b_ = simde__m512i_to_private(b); simde__mmask64 r = 0; - #if defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #if defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) simde__m512i_private tmp; tmp.i8 = HEDLEY_STATIC_CAST(__typeof__(tmp.i8), a_.i8 <= b_.i8); @@ -77,7 +77,7 @@ simde_mm512_cmple_epu8_mask (simde__m512i a, simde__m512i b) { b_ = simde__m512i_to_private(b); simde__mmask64 r = 0; - #if defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #if defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) simde__m512i_private tmp; tmp.i8 = HEDLEY_STATIC_CAST(__typeof__(tmp.i8), a_.u8 <= b_.u8); diff --git a/simde/x86/avx512/cmplt.h b/simde/x86/avx512/cmplt.h index 49dbe29cf..063cb3d58 100644 --- a/simde/x86/avx512/cmplt.h +++ b/simde/x86/avx512/cmplt.h @@ -66,7 +66,7 @@ simde_mm512_cmplt_epi8_mask (simde__m512i a, simde__m512i b) { b_ = simde__m512i_to_private(b); simde__mmask64 r = 0; - #if defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #if defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) simde__m512i_private tmp; tmp.i8 = HEDLEY_STATIC_CAST(__typeof__(tmp.i8), a_.i8 < b_.i8); @@ -97,7 +97,7 @@ simde_mm512_cmplt_epu8_mask (simde__m512i a, simde__m512i b) { b_ = simde__m512i_to_private(b); simde__mmask64 r = 0; - #if defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #if defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) simde__m512i_private tmp; tmp.i8 = HEDLEY_STATIC_CAST(__typeof__(tmp.i8), a_.u8 < b_.u8); diff --git a/simde/x86/avx512/permutex2var.h b/simde/x86/avx512/permutex2var.h index 6c26d25e2..70fe23230 100644 --- a/simde/x86/avx512/permutex2var.h +++ b/simde/x86/avx512/permutex2var.h @@ -703,8 +703,8 @@ simde_mm256_permutex2var_epi16 (simde__m256i a, simde__m256i idx, simde__m256i b _mm256_castsi256_ps(tb), _mm256_castsi256_ps(select))); - lo = _mm256_blend_epi16(_mm256_slli_epi32(hilo2, 16), hilo, 0x55); - hi = _mm256_blend_epi16(hilo2, _mm256_srli_epi32(hilo, 16), 0x55); + lo = simde_mm256_blend_epi16(_mm256_slli_epi32(hilo2, 16), hilo, 0x55); + hi = simde_mm256_blend_epi16(hilo2, _mm256_srli_epi32(hilo, 16), 0x55); select = _mm256_cmpeq_epi16(_mm256_and_si256(idx, ones), ones); return _mm256_blendv_epi8(lo, hi, select); @@ -1178,8 +1178,8 @@ simde_mm512_permutex2var_epi16 (simde__m512i a, simde__m512i idx, simde__m512i b _mm256_castsi256_ps(hilo2), _mm256_castsi256_ps(select))); - lo = _mm256_blend_epi16(_mm256_slli_epi32(hilo2, 16), hilo1, 0x55); - hi = _mm256_blend_epi16(hilo2, _mm256_srli_epi32(hilo1, 16), 0x55); + lo = simde_mm256_blend_epi16(_mm256_slli_epi32(hilo2, 16), hilo1, 0x55); + hi = simde_mm256_blend_epi16(hilo2, _mm256_srli_epi32(hilo1, 16), 0x55); select = _mm256_cmpeq_epi16(_mm256_and_si256(idx1, ones), ones); r_.m256i[i] = _mm256_blendv_epi8(lo, hi, select); diff --git a/simde/x86/avx512/sllv.h b/simde/x86/avx512/sllv.h index 9a0d5ed22..4c6e46c88 100644 --- a/simde/x86/avx512/sllv.h +++ b/simde/x86/avx512/sllv.h @@ -43,7 +43,7 @@ simde_mm512_sllv_epi16 (simde__m512i a, simde__m512i b) { b_ = simde__m512i_to_private(b), r_; - #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.u16 = HEDLEY_STATIC_CAST(__typeof__(r_.u16), (b_.u16 < 16) & (a_.u16 << b_.u16)); #else SIMDE_VECTORIZE diff --git a/simde/x86/avx512/srl.h b/simde/x86/avx512/srl.h index baf4a1923..97bb54356 100644 --- a/simde/x86/avx512/srl.h +++ b/simde/x86/avx512/srl.h @@ -58,7 +58,7 @@ simde_mm512_srl_epi16 (simde__m512i a, simde__m128i count) { if (HEDLEY_STATIC_CAST(uint64_t, count_.i64[0]) > 15) return simde_mm512_setzero_si512(); - #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.u16 = a_.u16 >> count_.i64[0]; #else SIMDE_VECTORIZE @@ -97,7 +97,7 @@ simde_mm512_srl_epi32 (simde__m512i a, simde__m128i count) { if (HEDLEY_STATIC_CAST(uint64_t, count_.i64[0]) > 31) return simde_mm512_setzero_si512(); - #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.u32 = a_.u32 >> count_.i64[0]; #else SIMDE_VECTORIZE @@ -164,7 +164,7 @@ simde_mm512_srl_epi64 (simde__m512i a, simde__m128i count) { if (HEDLEY_STATIC_CAST(uint64_t, count_.i64[0]) > 63) return simde_mm512_setzero_si512(); - #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.u64 = a_.u64 >> count_.i64[0]; #else SIMDE_VECTORIZE diff --git a/simde/x86/avx512/srlv.h b/simde/x86/avx512/srlv.h index 6f751c96b..2df04d8ed 100644 --- a/simde/x86/avx512/srlv.h +++ b/simde/x86/avx512/srlv.h @@ -47,7 +47,7 @@ simde_mm_srlv_epi16 (simde__m128i a, simde__m128i b) { b_ = simde__m128i_to_private(b), r_; - #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.u16 = HEDLEY_STATIC_CAST(__typeof__(r_.u16), (b_.u16 < 16) & (a_.u16 >> b_.u16)); #else SIMDE_VECTORIZE @@ -163,7 +163,7 @@ simde_mm256_srlv_epi16 (simde__m256i a, simde__m256i b) { for (size_t i = 0 ; i < (sizeof(r_.m128i) / sizeof(r_.m128i[0])) ; i++) { r_.m128i[i] = simde_mm_srlv_epi16(a_.m128i[i], b_.m128i[i]); } - #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.u16 = HEDLEY_STATIC_CAST(__typeof__(r_.u16), (b_.u16 < 16) & (a_.u16 >> b_.u16)); #else SIMDE_VECTORIZE @@ -195,7 +195,7 @@ simde_mm512_srlv_epi16 (simde__m512i a, simde__m512i b) { for (size_t i = 0 ; i < (sizeof(r_.m256i) / sizeof(r_.m256i[0])) ; i++) { r_.m256i[i] = simde_mm256_srlv_epi16(a_.m256i[i], b_.m256i[i]); } - #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.u16 = HEDLEY_STATIC_CAST(__typeof__(r_.u16), (b_.u16 < 16) & (a_.u16 >> b_.u16)); #else SIMDE_VECTORIZE @@ -227,7 +227,7 @@ simde_mm512_srlv_epi32 (simde__m512i a, simde__m512i b) { for (size_t i = 0 ; i < (sizeof(r_.m256i) / sizeof(r_.m256i[0])) ; i++) { r_.m256i[i] = simde_mm256_srlv_epi32(a_.m256i[i], b_.m256i[i]); } - #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.u32 = HEDLEY_STATIC_CAST(__typeof__(r_.u32), (b_.u32 < 32) & (a_.u32 >> b_.u32)); #else SIMDE_VECTORIZE @@ -259,7 +259,7 @@ simde_mm512_srlv_epi64 (simde__m512i a, simde__m512i b) { for (size_t i = 0 ; i < (sizeof(r_.m256i) / sizeof(r_.m256i[0])) ; i++) { r_.m256i[i] = simde_mm256_srlv_epi64(a_.m256i[i], b_.m256i[i]); } - #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.u64 = HEDLEY_STATIC_CAST(__typeof__(r_.u64), (b_.u64 < 64) & (a_.u64 >> b_.u64)); #else SIMDE_VECTORIZE diff --git a/simde/x86/avx512/types.h b/simde/x86/avx512/types.h index 7df5204f4..11c5d032d 100644 --- a/simde/x86/avx512/types.h +++ b/simde/x86/avx512/types.h @@ -116,7 +116,7 @@ typedef union { SIMDE_ALIGN_TO_16 SIMDE_POWER_ALTIVEC_VECTOR(double) altivec_f64[4]; #endif #endif -} simde__m512_private; +} SIMDE_ALIGN_REDUCE_STRUCT simde__m512_private; typedef union { #if defined(SIMDE_VECTOR_SUBSCRIPT) @@ -176,7 +176,7 @@ typedef union { SIMDE_ALIGN_TO_16 SIMDE_POWER_ALTIVEC_VECTOR(double) altivec_f64[4]; #endif #endif -} simde__m512d_private; +} SIMDE_ALIGN_REDUCE_STRUCT simde__m512d_private; typedef union { #if defined(SIMDE_VECTOR_SUBSCRIPT) @@ -236,7 +236,7 @@ typedef union { SIMDE_ALIGN_TO_16 SIMDE_POWER_ALTIVEC_VECTOR(double) altivec_f64[4]; #endif #endif -} simde__m512i_private; +} SIMDE_ALIGN_REDUCE_STRUCT simde__m512i_private; /* Intel uses the same header (immintrin.h) for everything AVX and * later. If native aliases are enabled, and the machine has native diff --git a/simde/x86/clmul.h b/simde/x86/clmul.h index e2bf77f99..d6c6fe5e0 100644 --- a/simde/x86/clmul.h +++ b/simde/x86/clmul.h @@ -203,8 +203,21 @@ simde_mm_clmulepi64_si128 (simde__m128i a, simde__m128i b, const int imm8) return simde__m128i_from_private(r_); } + +#if defined(SIMDE_X86_PCLMUL_NATIVE) && defined(SIMDE_BUG_PCLMUL_XOP_DEPRECATED) + SIMDE_LCC_DISABLE_DEPRECATED_WARNINGS + SIMDE_FUNCTION_ATTRIBUTES + simde__m128i + simde_undeprecated_mm_clmulepi64_si128 (simde__m128i a, simde__m128i b, const int imm8) { + return _mm_clmulepi64_si128(a, b, imm8); + } + SIMDE_LCC_REVERT_DEPRECATED_WARNINGS +#else + #define simde_undeprecated_mm_clmulepi64_si128 _mm_clmulepi64_si128 +#endif + #if defined(SIMDE_X86_PCLMUL_NATIVE) - #define simde_mm_clmulepi64_si128(a, b, imm8) _mm_clmulepi64_si128(a, b, imm8) + #define simde_mm_clmulepi64_si128(a, b, imm8) simde_undeprecated_mm_clmulepi64_si128(a, b, imm8) #elif defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(__ARM_FEATURE_AES) #define simde_mm_clmulepi64_si128(a, b, imm8) \ simde__m128i_from_neon_u64( \ @@ -233,20 +246,20 @@ simde_mm256_clmulepi64_epi128 (simde__m256i a, simde__m256i b, const int imm8) #if defined(SIMDE_X86_PCLMUL_NATIVE) switch (imm8 & 0x11) { case 0x00: - r_.m128i[0] = _mm_clmulepi64_si128(a_.m128i[0], b_.m128i[0], 0x00); - r_.m128i[1] = _mm_clmulepi64_si128(a_.m128i[1], b_.m128i[1], 0x00); + r_.m128i[0] = simde_undeprecated_mm_clmulepi64_si128(a_.m128i[0], b_.m128i[0], 0x00); + r_.m128i[1] = simde_undeprecated_mm_clmulepi64_si128(a_.m128i[1], b_.m128i[1], 0x00); break; case 0x01: - r_.m128i[0] = _mm_clmulepi64_si128(a_.m128i[0], b_.m128i[0], 0x01); - r_.m128i[1] = _mm_clmulepi64_si128(a_.m128i[1], b_.m128i[1], 0x01); + r_.m128i[0] = simde_undeprecated_mm_clmulepi64_si128(a_.m128i[0], b_.m128i[0], 0x01); + r_.m128i[1] = simde_undeprecated_mm_clmulepi64_si128(a_.m128i[1], b_.m128i[1], 0x01); break; case 0x10: - r_.m128i[0] = _mm_clmulepi64_si128(a_.m128i[0], b_.m128i[0], 0x10); - r_.m128i[1] = _mm_clmulepi64_si128(a_.m128i[1], b_.m128i[1], 0x10); + r_.m128i[0] = simde_undeprecated_mm_clmulepi64_si128(a_.m128i[0], b_.m128i[0], 0x10); + r_.m128i[1] = simde_undeprecated_mm_clmulepi64_si128(a_.m128i[1], b_.m128i[1], 0x10); break; case 0x11: - r_.m128i[0] = _mm_clmulepi64_si128(a_.m128i[0], b_.m128i[0], 0x11); - r_.m128i[1] = _mm_clmulepi64_si128(a_.m128i[1], b_.m128i[1], 0x11); + r_.m128i[0] = simde_undeprecated_mm_clmulepi64_si128(a_.m128i[0], b_.m128i[0], 0x11); + r_.m128i[1] = simde_undeprecated_mm_clmulepi64_si128(a_.m128i[1], b_.m128i[1], 0x11); break; } #else diff --git a/simde/x86/f16c.h b/simde/x86/f16c.h index ecbb748fd..27afddc2b 100644 --- a/simde/x86/f16c.h +++ b/simde/x86/f16c.h @@ -45,12 +45,14 @@ SIMDE_FUNCTION_ATTRIBUTES simde__m128i simde_mm_cvtps_ph(simde__m128 a, const int sae) { #if defined(SIMDE_X86_F16C_NATIVE) + SIMDE_LCC_DISABLE_DEPRECATED_WARNINGS switch (sae & SIMDE_MM_FROUND_NO_EXC) { case SIMDE_MM_FROUND_NO_EXC: return _mm_cvtps_ph(a, SIMDE_MM_FROUND_NO_EXC); default: return _mm_cvtps_ph(a, 0); } + SIMDE_LCC_REVERT_DEPRECATED_WARNINGS #else simde__m128_private a_ = simde__m128_to_private(a); simde__m128i_private r_ = simde__m128i_to_private(simde_mm_setzero_si128()); @@ -102,12 +104,14 @@ SIMDE_FUNCTION_ATTRIBUTES simde__m128i simde_mm256_cvtps_ph(simde__m256 a, const int sae) { #if defined(SIMDE_X86_F16C_NATIVE) && defined(SIMDE_X86_AVX_NATIVE) + SIMDE_LCC_DISABLE_DEPRECATED_WARNINGS switch (sae & SIMDE_MM_FROUND_NO_EXC) { case SIMDE_MM_FROUND_NO_EXC: return _mm256_cvtps_ph(a, SIMDE_MM_FROUND_NO_EXC); default: return _mm256_cvtps_ph(a, 0); } + SIMDE_LCC_REVERT_DEPRECATED_WARNINGS #else simde__m256_private a_ = simde__m256_to_private(a); simde__m128i_private r_; diff --git a/simde/x86/fma.h b/simde/x86/fma.h index e43a45d5e..0221c76a3 100644 --- a/simde/x86/fma.h +++ b/simde/x86/fma.h @@ -156,7 +156,7 @@ simde_mm256_fmadd_ps (simde__m256 a, simde__m256 b, simde__m256 c) { SIMDE_FUNCTION_ATTRIBUTES simde__m128d simde_mm_fmadd_sd (simde__m128d a, simde__m128d b, simde__m128d c) { - #if defined(SIMDE_X86_FMA_NATIVE) + #if defined(SIMDE_X86_FMA_NATIVE) && !defined(SIMDE_BUG_LCC_FMA_WRONG_RESULT) return _mm_fmadd_sd(a, b, c); #else return simde_mm_add_sd(simde_mm_mul_sd(a, b), c); @@ -170,7 +170,7 @@ simde_mm_fmadd_sd (simde__m128d a, simde__m128d b, simde__m128d c) { SIMDE_FUNCTION_ATTRIBUTES simde__m128 simde_mm_fmadd_ss (simde__m128 a, simde__m128 b, simde__m128 c) { - #if defined(SIMDE_X86_FMA_NATIVE) + #if defined(SIMDE_X86_FMA_NATIVE) && !defined(SIMDE_BUG_LCC_FMA_WRONG_RESULT) return _mm_fmadd_ss(a, b, c); #else return simde_mm_add_ss(simde_mm_mul_ss(a, b), c); @@ -296,7 +296,7 @@ simde_mm256_fmsub_ps (simde__m256 a, simde__m256 b, simde__m256 c) { SIMDE_FUNCTION_ATTRIBUTES simde__m128d simde_mm_fmsub_sd (simde__m128d a, simde__m128d b, simde__m128d c) { - #if defined(SIMDE_X86_FMA_NATIVE) + #if defined(SIMDE_X86_FMA_NATIVE) && !defined(SIMDE_BUG_LCC_FMA_WRONG_RESULT) return _mm_fmsub_sd(a, b, c); #else return simde_mm_sub_sd(simde_mm_mul_sd(a, b), c); @@ -310,7 +310,7 @@ simde_mm_fmsub_sd (simde__m128d a, simde__m128d b, simde__m128d c) { SIMDE_FUNCTION_ATTRIBUTES simde__m128 simde_mm_fmsub_ss (simde__m128 a, simde__m128 b, simde__m128 c) { - #if defined(SIMDE_X86_FMA_NATIVE) + #if defined(SIMDE_X86_FMA_NATIVE) && !defined(SIMDE_BUG_LCC_FMA_WRONG_RESULT) return _mm_fmsub_ss(a, b, c); #else return simde_mm_sub_ss(simde_mm_mul_ss(a, b), c); @@ -528,7 +528,7 @@ simde_mm256_fnmadd_ps (simde__m256 a, simde__m256 b, simde__m256 c) { SIMDE_FUNCTION_ATTRIBUTES simde__m128d simde_mm_fnmadd_sd (simde__m128d a, simde__m128d b, simde__m128d c) { - #if defined(SIMDE_X86_FMA_NATIVE) + #if defined(SIMDE_X86_FMA_NATIVE) && !defined(SIMDE_BUG_LCC_FMA_WRONG_RESULT) return _mm_fnmadd_sd(a, b, c); #else simde__m128d_private @@ -551,7 +551,7 @@ simde_mm_fnmadd_sd (simde__m128d a, simde__m128d b, simde__m128d c) { SIMDE_FUNCTION_ATTRIBUTES simde__m128 simde_mm_fnmadd_ss (simde__m128 a, simde__m128 b, simde__m128 c) { - #if defined(SIMDE_X86_FMA_NATIVE) + #if defined(SIMDE_X86_FMA_NATIVE) && !defined(SIMDE_BUG_LCC_FMA_WRONG_RESULT) return _mm_fnmadd_ss(a, b, c); #else simde__m128_private @@ -674,7 +674,7 @@ simde_mm256_fnmsub_ps (simde__m256 a, simde__m256 b, simde__m256 c) { SIMDE_FUNCTION_ATTRIBUTES simde__m128d simde_mm_fnmsub_sd (simde__m128d a, simde__m128d b, simde__m128d c) { - #if defined(SIMDE_X86_FMA_NATIVE) + #if defined(SIMDE_X86_FMA_NATIVE) && !defined(SIMDE_BUG_LCC_FMA_WRONG_RESULT) return _mm_fnmsub_sd(a, b, c); #else simde__m128d_private @@ -697,7 +697,7 @@ simde_mm_fnmsub_sd (simde__m128d a, simde__m128d b, simde__m128d c) { SIMDE_FUNCTION_ATTRIBUTES simde__m128 simde_mm_fnmsub_ss (simde__m128 a, simde__m128 b, simde__m128 c) { - #if defined(SIMDE_X86_FMA_NATIVE) + #if defined(SIMDE_X86_FMA_NATIVE) && !defined(SIMDE_BUG_LCC_FMA_WRONG_RESULT) return _mm_fnmsub_ss(a, b, c); #else simde__m128_private diff --git a/simde/x86/mmx.h b/simde/x86/mmx.h index 2d2f6d730..8826233f8 100644 --- a/simde/x86/mmx.h +++ b/simde/x86/mmx.h @@ -1395,7 +1395,7 @@ simde_mm_sll_pi16 (simde__m64 a, simde__m64 count) { return simde_mm_setzero_si64(); r_.i16 = a_.i16 << HEDLEY_STATIC_CAST(int16_t, count_.u64[0]); - #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.i16 = a_.i16 << count_.u64[0]; #else if (HEDLEY_UNLIKELY(count_.u64[0] > 15)) { @@ -1435,7 +1435,7 @@ simde_mm_sll_pi32 (simde__m64 a, simde__m64 count) { #endif r_.neon_i32 = vshl_s32(a_.neon_i32, vmov_n_s32(HEDLEY_STATIC_CAST(int32_t, vget_lane_u64(count_.neon_u64, 0)))); HEDLEY_DIAGNOSTIC_POP - #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.i32 = a_.i32 << count_.u64[0]; #else if (HEDLEY_UNLIKELY(count_.u64[0] > 31)) { @@ -1472,7 +1472,7 @@ simde_mm_slli_pi16 (simde__m64 a, int count) { return simde_mm_setzero_si64(); r_.i16 = a_.i16 << HEDLEY_STATIC_CAST(int16_t, count); - #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.i16 = a_.i16 << count; #elif defined(SIMDE_ARM_NEON_A32V7_NATIVE) r_.neon_i16 = vshl_s16(a_.neon_i16, vmov_n_s16((int16_t) count)); @@ -1598,7 +1598,7 @@ simde_mm_srl_pi16 (simde__m64 a, simde__m64 count) { return simde_mm_setzero_si64(); r_.i16 = a_.i16 >> HEDLEY_STATIC_CAST(int16_t, count_.u64[0]); - #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.u16 = a_.u16 >> count_.u64[0]; #elif defined(SIMDE_ARM_NEON_A32V7_NATIVE) r_.neon_u16 = vshl_u16(a_.neon_u16, vmov_n_s16(-((int16_t) vget_lane_u64(count_.neon_u64, 0)))); @@ -1633,7 +1633,7 @@ simde_mm_srl_pi32 (simde__m64 a, simde__m64 count) { simde__m64_private a_ = simde__m64_to_private(a); simde__m64_private count_ = simde__m64_to_private(count); - #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.u32 = a_.u32 >> count_.u64[0]; #elif defined(SIMDE_ARM_NEON_A32V7_NATIVE) r_.neon_u32 = vshl_u32(a_.neon_u32, vmov_n_s32(-((int32_t) vget_lane_u64(count_.neon_u64, 0)))); @@ -1667,7 +1667,7 @@ simde_mm_srli_pi16 (simde__m64 a, int count) { simde__m64_private r_; simde__m64_private a_ = simde__m64_to_private(a); - #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.u16 = a_.u16 >> count; #elif defined(SIMDE_ARM_NEON_A32V7_NATIVE) r_.neon_u16 = vshl_u16(a_.neon_u16, vmov_n_s16(-((int16_t) count))); @@ -1698,7 +1698,7 @@ simde_mm_srli_pi32 (simde__m64 a, int count) { simde__m64_private r_; simde__m64_private a_ = simde__m64_to_private(a); - #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.u32 = a_.u32 >> count; #elif defined(SIMDE_ARM_NEON_A32V7_NATIVE) r_.neon_u32 = vshl_u32(a_.neon_u32, vmov_n_s32(-((int32_t) count))); @@ -1731,7 +1731,7 @@ simde_mm_srli_si64 (simde__m64 a, int count) { #if defined(SIMDE_ARM_NEON_A32V7_NATIVE) r_.neon_u64 = vshl_u64(a_.neon_u64, vmov_n_s64(-count)); - #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.u64 = a_.u64 >> count; #else r_.u64[0] = a_.u64[0] >> count; @@ -1787,7 +1787,7 @@ simde_mm_srai_pi16 (simde__m64 a, int count) { simde__m64_private r_; simde__m64_private a_ = simde__m64_to_private(a); - #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.i16 = a_.i16 >> (count & 0xff); #elif defined(SIMDE_ARM_NEON_A32V7_NATIVE) r_.neon_i16 = vshl_s16(a_.neon_i16, vmov_n_s16(-HEDLEY_STATIC_CAST(int16_t, count))); @@ -1851,7 +1851,7 @@ simde_mm_sra_pi16 (simde__m64 a, simde__m64 count) { simde__m64_private count_ = simde__m64_to_private(count); const int cnt = HEDLEY_STATIC_CAST(int, (count_.i64[0] > 15 ? 15 : count_.i64[0])); - #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.i16 = a_.i16 >> cnt; #elif defined(SIMDE_ARM_NEON_A32V7_NATIVE) r_.neon_i16 = vshl_s16(a_.neon_i16, vmov_n_s16(-HEDLEY_STATIC_CAST(int16_t, vget_lane_u64(count_.neon_u64, 0)))); diff --git a/simde/x86/sse2.h b/simde/x86/sse2.h index 88fa92217..9d6467a4b 100644 --- a/simde/x86/sse2.h +++ b/simde/x86/sse2.h @@ -1180,7 +1180,11 @@ simde_mm_bslli_si128 (simde__m128i a, const int imm8) return simde__m128i_from_private(r_); } #if defined(SIMDE_X86_SSE2_NATIVE) && !defined(__PGI) - #define simde_mm_bslli_si128(a, imm8) _mm_slli_si128(a, imm8) + #if defined(SIMDE_BUG_LCC_WARNING_ON_SHIFTS) + #define simde_mm_bslli_si128(a, imm8) ((imm8 & ~15) ? _mm_setzero_si128() : _mm_slli_si128(a, imm8 & 15)) + #else + #define simde_mm_bslli_si128(a, imm8) _mm_slli_si128(a, imm8) + #endif #elif defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(__clang__) #define simde_mm_bslli_si128(a, imm8) \ simde__m128i_from_neon_i8(((imm8) <= 0) ? simde__m128i_to_neon_i8(a) : (((imm8) > 15) ? (vdupq_n_s8(0)) : (vextq_s8(vdupq_n_s8(0), simde__m128i_to_neon_i8(a), 16 - (imm8))))) @@ -1252,7 +1256,11 @@ simde_mm_bsrli_si128 (simde__m128i a, const int imm8) return simde__m128i_from_private(r_); } #if defined(SIMDE_X86_SSE2_NATIVE) && !defined(__PGI) - #define simde_mm_bsrli_si128(a, imm8) _mm_srli_si128(a, imm8) + #if defined(SIMDE_BUG_LCC_WARNING_ON_SHIFTS) + #define simde_mm_bsrli_si128(a, imm8) ((imm8 & ~15) ? _mm_setzero_si128() : _mm_srli_si128(a, imm8 & 15)) + #else + #define simde_mm_bsrli_si128(a, imm8) _mm_srli_si128(a, imm8) + #endif #elif defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(__clang__) #define simde_mm_bsrli_si128(a, imm8) \ simde__m128i_from_neon_i8(((imm8 < 0) || (imm8 > 15)) ? vdupq_n_s8(0) : (vextq_s8(simde__m128i_to_private(a).neon_i8, vdupq_n_s8(0), ((imm8 & 15) != 0) ? imm8 : (imm8 & 15)))) @@ -1602,7 +1610,7 @@ simde_mm_cmpeq_epi8 (simde__m128i a, simde__m128i b) { r_.wasm_v128 = wasm_i8x16_eq(a_.wasm_v128, b_.wasm_v128); #elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE) r_.altivec_i8 = HEDLEY_REINTERPRET_CAST(SIMDE_POWER_ALTIVEC_VECTOR(signed char), vec_cmpeq(a_.altivec_i8, b_.altivec_i8)); - #elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.i8 = HEDLEY_STATIC_CAST(__typeof__(r_.i8), (a_.i8 == b_.i8)); #else SIMDE_VECTORIZE @@ -1812,7 +1820,7 @@ simde_mm_cmplt_epi8 (simde__m128i a, simde__m128i b) { r_.altivec_i8 = HEDLEY_REINTERPRET_CAST(SIMDE_POWER_ALTIVEC_VECTOR(signed char),vec_cmplt(a_.altivec_i8, b_.altivec_i8)); #elif defined(SIMDE_WASM_SIMD128_NATIVE) r_.wasm_v128 = wasm_i8x16_lt(a_.wasm_v128, b_.wasm_v128); - #elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.i8 = HEDLEY_STATIC_CAST(__typeof__(r_.i8), (a_.i8 < b_.i8)); #else SIMDE_VECTORIZE @@ -2021,7 +2029,7 @@ simde_mm_cmpgt_epi8 (simde__m128i a, simde__m128i b) { r_.wasm_v128 = wasm_i8x16_gt(a_.wasm_v128, b_.wasm_v128); #elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE) r_.altivec_i8 = HEDLEY_REINTERPRET_CAST(SIMDE_POWER_ALTIVEC_VECTOR(signed char), vec_cmpgt(a_.altivec_i8, b_.altivec_i8)); - #elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.i8 = HEDLEY_STATIC_CAST(__typeof__(r_.i8), (a_.i8 > b_.i8)); #else SIMDE_VECTORIZE @@ -5346,7 +5354,7 @@ simde_mm_sll_epi16 (simde__m128i a, simde__m128i count) { if (count_.u64[0] > 15) return simde_mm_setzero_si128(); - #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.u16 = (a_.u16 << count_.u64[0]); #elif defined(SIMDE_ARM_NEON_A32V7_NATIVE) r_.neon_u16 = vshlq_u16(a_.neon_u16, vdupq_n_s16(HEDLEY_STATIC_CAST(int16_t, count_.u64[0]))); @@ -5380,7 +5388,7 @@ simde_mm_sll_epi32 (simde__m128i a, simde__m128i count) { if (count_.u64[0] > 31) return simde_mm_setzero_si128(); - #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) r_.u32 = (a_.u32 << count_.u64[0]); #elif defined(SIMDE_ARM_NEON_A32V7_NATIVE) r_.neon_u32 = vshlq_u32(a_.neon_u32, vdupq_n_s32(HEDLEY_STATIC_CAST(int32_t, count_.u64[0]))); diff --git a/simde/x86/sse4.1.h b/simde/x86/sse4.1.h index e93fbf8b3..c61510091 100644 --- a/simde/x86/sse4.1.h +++ b/simde/x86/sse4.1.h @@ -204,7 +204,7 @@ simde_mm_blendv_epi8 (simde__m128i a, simde__m128i b, simde__m128i mask) { r_.altivec_i8 = vec_sel(a_.altivec_i8, b_.altivec_i8, vec_cmplt(mask_.altivec_i8, vec_splat_s8(0))); #elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS) /* https://software.intel.com/en-us/forums/intel-c-compiler/topic/850087 */ - #if defined(HEDLEY_INTEL_VERSION_CHECK) && !defined(SIMDE_SKIP_EXTENDED_E2K_VECTOR_OPS) + #if defined(HEDLEY_INTEL_VERSION_CHECK) && !defined(SIMDE_BUG_LCC_TOO_STRICT_VECTOR_SHIFTS_AND_COMPARES) __typeof__(mask_.i8) z = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; mask_.i8 = HEDLEY_STATIC_CAST(__typeof__(mask_.i8), mask_.i8 < z); #else diff --git a/simde/x86/svml.h b/simde/x86/svml.h index 6c28ed7fb..5b5b2e7da 100644 --- a/simde/x86/svml.h +++ b/simde/x86/svml.h @@ -7133,7 +7133,7 @@ simde_mm256_erfcinv_ps (simde__m256 a) { t = simde_mm256_sqrt_ps(t); t = simde_mm256_div_ps(simde_mm256_set1_ps(SIMDE_FLOAT32_C(1.0)), t); - const simde__m256 p[] = { + const simde__m256 SIMDE_ALIGN_REDUCE_ARRAY p[] = { simde_mm256_set1_ps(SIMDE_FLOAT32_C( 0.1550470003116)), simde_mm256_set1_ps(SIMDE_FLOAT32_C( 1.382719649631)), simde_mm256_set1_ps(SIMDE_FLOAT32_C( 0.690969348887)), @@ -7142,7 +7142,7 @@ simde_mm256_erfcinv_ps (simde__m256 a) { simde_mm256_set1_ps(SIMDE_FLOAT32_C(-0.16444156791)) }; - const simde__m256 q[] = { + const simde__m256 SIMDE_ALIGN_REDUCE_ARRAY q[] = { simde_mm256_set1_ps(SIMDE_FLOAT32_C( 0.155024849822)), simde_mm256_set1_ps(SIMDE_FLOAT32_C( 1.385228141995)), simde_mm256_set1_ps(SIMDE_FLOAT32_C( 1.000000000000)) @@ -7177,14 +7177,14 @@ simde_mm256_erfcinv_ps (simde__m256 a) { t = simde_mm256_sqrt_ps(t); t = simde_mm256_div_ps(simde_mm256_set1_ps(SIMDE_FLOAT32_C(1.0)), t); - const simde__m256 p[] = { + const simde__m256 SIMDE_ALIGN_REDUCE_ARRAY p[] = { simde_mm256_set1_ps(SIMDE_FLOAT32_C( 0.00980456202915)), simde_mm256_set1_ps(SIMDE_FLOAT32_C( 0.36366788917100)), simde_mm256_set1_ps(SIMDE_FLOAT32_C( 0.97302949837000)), simde_mm256_set1_ps(SIMDE_FLOAT32_C(-0.5374947401000)) }; - const simde__m256 q[] = { + const simde__m256 SIMDE_ALIGN_REDUCE_ARRAY q[] = { simde_mm256_set1_ps(SIMDE_FLOAT32_C( 0.00980451277802)), simde_mm256_set1_ps(SIMDE_FLOAT32_C( 0.36369997154400)), simde_mm256_set1_ps(SIMDE_FLOAT32_C( 1.00000000000000)) @@ -7283,7 +7283,7 @@ simde_mm256_erfcinv_pd (simde__m256d a) { t = simde_mm256_sqrt_pd(t); t = simde_mm256_div_pd(simde_mm256_set1_pd(SIMDE_FLOAT64_C(1.0)), t); - const simde__m256d p[] = { + const simde__m256d SIMDE_ALIGN_REDUCE_ARRAY p[] = { simde_mm256_set1_pd(SIMDE_FLOAT64_C( 0.1550470003116)), simde_mm256_set1_pd(SIMDE_FLOAT64_C( 1.382719649631)), simde_mm256_set1_pd(SIMDE_FLOAT64_C( 0.690969348887)), @@ -7292,7 +7292,7 @@ simde_mm256_erfcinv_pd (simde__m256d a) { simde_mm256_set1_pd(SIMDE_FLOAT64_C(-0.16444156791)) }; - const simde__m256d q[] = { + const simde__m256d SIMDE_ALIGN_REDUCE_ARRAY q[] = { simde_mm256_set1_pd(SIMDE_FLOAT64_C( 0.155024849822)), simde_mm256_set1_pd(SIMDE_FLOAT64_C( 1.385228141995)), simde_mm256_set1_pd(SIMDE_FLOAT64_C( 1.000000000000)) @@ -7327,14 +7327,14 @@ simde_mm256_erfcinv_pd (simde__m256d a) { t = simde_mm256_sqrt_pd(t); t = simde_mm256_div_pd(simde_mm256_set1_pd(SIMDE_FLOAT64_C(1.0)), t); - const simde__m256d p[] = { + const simde__m256d SIMDE_ALIGN_REDUCE_ARRAY p[] = { simde_mm256_set1_pd(SIMDE_FLOAT64_C( 0.00980456202915)), simde_mm256_set1_pd(SIMDE_FLOAT64_C( 0.36366788917100)), simde_mm256_set1_pd(SIMDE_FLOAT64_C( 0.97302949837000)), simde_mm256_set1_pd(SIMDE_FLOAT64_C(-0.5374947401000)) }; - const simde__m256d q[] = { + const simde__m256d SIMDE_ALIGN_REDUCE_ARRAY q[] = { simde_mm256_set1_pd(SIMDE_FLOAT64_C( 0.00980451277802)), simde_mm256_set1_pd(SIMDE_FLOAT64_C( 0.36369997154400)), simde_mm256_set1_pd(SIMDE_FLOAT64_C( 1.00000000000000)) @@ -7446,7 +7446,7 @@ simde_mm512_erfcinv_ps (simde__m512 a) { t = simde_mm512_sqrt_ps(t); t = simde_mm512_div_ps(simde_mm512_set1_ps(SIMDE_FLOAT32_C(1.0)), t); - const simde__m512 p[] = { + const simde__m512 SIMDE_ALIGN_REDUCE_ARRAY p[] = { simde_mm512_set1_ps(SIMDE_FLOAT32_C( 0.1550470003116)), simde_mm512_set1_ps(SIMDE_FLOAT32_C( 1.382719649631)), simde_mm512_set1_ps(SIMDE_FLOAT32_C( 0.690969348887)), @@ -7455,7 +7455,7 @@ simde_mm512_erfcinv_ps (simde__m512 a) { simde_mm512_set1_ps(SIMDE_FLOAT32_C(-0.16444156791)) }; - const simde__m512 q[] = { + const simde__m512 SIMDE_ALIGN_REDUCE_ARRAY q[] = { simde_mm512_set1_ps(SIMDE_FLOAT32_C( 0.155024849822)), simde_mm512_set1_ps(SIMDE_FLOAT32_C( 1.385228141995)), simde_mm512_set1_ps(SIMDE_FLOAT32_C( 1.000000000000)) @@ -7490,14 +7490,14 @@ simde_mm512_erfcinv_ps (simde__m512 a) { t = simde_mm512_sqrt_ps(t); t = simde_mm512_div_ps(simde_mm512_set1_ps(SIMDE_FLOAT32_C(1.0)), t); - const simde__m512 p[] = { + const simde__m512 SIMDE_ALIGN_REDUCE_ARRAY p[] = { simde_mm512_set1_ps(SIMDE_FLOAT32_C( 0.00980456202915)), simde_mm512_set1_ps(SIMDE_FLOAT32_C( 0.36366788917100)), simde_mm512_set1_ps(SIMDE_FLOAT32_C( 0.97302949837000)), simde_mm512_set1_ps(SIMDE_FLOAT32_C( -0.5374947401000)) }; - const simde__m512 q[] = { + const simde__m512 SIMDE_ALIGN_REDUCE_ARRAY q[] = { simde_mm512_set1_ps(SIMDE_FLOAT32_C( 0.00980451277802)), simde_mm512_set1_ps(SIMDE_FLOAT32_C( 0.36369997154400)), simde_mm512_set1_ps(SIMDE_FLOAT32_C( 1.00000000000000)) @@ -7589,7 +7589,7 @@ simde_mm512_erfcinv_pd (simde__m512d a) { t = simde_mm512_sqrt_pd(t); t = simde_mm512_div_pd(simde_mm512_set1_pd(SIMDE_FLOAT64_C(1.0)), t); - const simde__m512d p[] = { + const simde__m512d SIMDE_ALIGN_REDUCE_ARRAY p[] = { simde_mm512_set1_pd(SIMDE_FLOAT64_C( 0.1550470003116)), simde_mm512_set1_pd(SIMDE_FLOAT64_C( 1.382719649631)), simde_mm512_set1_pd(SIMDE_FLOAT64_C( 0.690969348887)), @@ -7598,7 +7598,7 @@ simde_mm512_erfcinv_pd (simde__m512d a) { simde_mm512_set1_pd(SIMDE_FLOAT64_C(-0.16444156791)) }; - const simde__m512d q[] = { + const simde__m512d SIMDE_ALIGN_REDUCE_ARRAY q[] = { simde_mm512_set1_pd(SIMDE_FLOAT64_C( 0.155024849822)), simde_mm512_set1_pd(SIMDE_FLOAT64_C( 1.385228141995)), simde_mm512_set1_pd(SIMDE_FLOAT64_C( 1.000000000000)) @@ -7633,14 +7633,14 @@ simde_mm512_erfcinv_pd (simde__m512d a) { t = simde_mm512_sqrt_pd(t); t = simde_mm512_div_pd(simde_mm512_set1_pd(SIMDE_FLOAT64_C(1.0)), t); - const simde__m512d p[] = { + const simde__m512d SIMDE_ALIGN_REDUCE_ARRAY p[] = { simde_mm512_set1_pd(SIMDE_FLOAT64_C( 0.00980456202915)), simde_mm512_set1_pd(SIMDE_FLOAT64_C( 0.36366788917100)), simde_mm512_set1_pd(SIMDE_FLOAT64_C( 0.97302949837000)), simde_mm512_set1_pd(SIMDE_FLOAT64_C( -0.5374947401000)) }; - const simde__m512d q[] = { + const simde__m512d SIMDE_ALIGN_REDUCE_ARRAY q[] = { simde_mm512_set1_pd(SIMDE_FLOAT64_C( 0.00980451277802)), simde_mm512_set1_pd(SIMDE_FLOAT64_C( 0.36369997154400)), simde_mm512_set1_pd(SIMDE_FLOAT64_C( 1.00000000000000)) diff --git a/simde/x86/xop.h b/simde/x86/xop.h index 839f1a427..94e0eae9a 100644 --- a/simde/x86/xop.h +++ b/simde/x86/xop.h @@ -78,7 +78,7 @@ simde_mm_cmov_si128 (simde__m128i a, simde__m128i b, simde__m128i c) { SIMDE_FUNCTION_ATTRIBUTES simde__m256i simde_mm256_cmov_si256 (simde__m256i a, simde__m256i b, simde__m256i c) { - #if defined(SIMDE_X86_XOP_NATIVE) && defined(SIMDE_X86_AVX_NATIVE) && !defined(SIMDE_BUG_GCC_98521) + #if defined(SIMDE_X86_XOP_NATIVE) && defined(SIMDE_X86_AVX_NATIVE) && !defined(SIMDE_BUG_GCC_98521) && !defined(SIMDE_BUG_LCC_XOP_MISSING) return _mm256_cmov_si256(a, b, c); #elif defined(SIMDE_X86_AVX512VL_NATIVE) return _mm256_ternarylogic_epi32(a, b, c, 0xe4); @@ -3511,8 +3511,21 @@ simde_mm_permute2_ps (simde__m128 a, simde__m128 b, simde__m128i c, const int im return simde__m128_from_private(r_); } + +#if defined(SIMDE_X86_XOP_NATIVE) && defined(SIMDE_BUG_PCLMUL_XOP_DEPRECATED) + SIMDE_LCC_DISABLE_DEPRECATED_WARNINGS + SIMDE_FUNCTION_ATTRIBUTES + simde__m128 + simde_undeprecated_mm_permute2_ps (simde__m128 a, simde__m128 b, simde__m128i c, const int imm8) { + return _mm_permute2_ps(a, b, c, imm8); + } + SIMDE_LCC_REVERT_DEPRECATED_WARNINGS +#else + #define simde_undeprecated_mm_permute2_ps _mm_permute2_ps +#endif + #if defined(SIMDE_X86_XOP_NATIVE) - #define simde_mm_permute2_ps(a, b, c, imm8) _mm_permute2_ps((a), (b), (c), (imm8)) + #define simde_mm_permute2_ps(a, b, c, imm8) simde_undeprecated_mm_permute2_ps((a), (b), (c), (imm8)) #endif #if defined(SIMDE_X86_XOP_ENABLE_NATIVE_ALIASES) #define _mm_permute2_ps(a, b, c, imm8) simde_mm_permute2_ps((a), (b), (c), (imm8)) @@ -3547,8 +3560,21 @@ simde_mm_permute2_pd (simde__m128d a, simde__m128d b, simde__m128i c, const int return simde__m128d_from_private(r_); } + +#if defined(SIMDE_X86_XOP_NATIVE) && defined(SIMDE_BUG_PCLMUL_XOP_DEPRECATED) + SIMDE_LCC_DISABLE_DEPRECATED_WARNINGS + SIMDE_FUNCTION_ATTRIBUTES + simde__m128d + simde_undeprecated_mm_permute2_pd (simde__m128d a, simde__m128d b, simde__m128i c, const int imm8) { + return _mm_permute2_pd(a, b, c, imm8); + } + SIMDE_LCC_REVERT_DEPRECATED_WARNINGS +#else + #define simde_undeprecated_mm_permute2_pd _mm_permute2_pd +#endif + #if defined(SIMDE_X86_XOP_NATIVE) - #define simde_mm_permute2_pd(a, b, c, imm8) _mm_permute2_pd((a), (b), (c), (imm8)) + #define simde_mm_permute2_pd(a, b, c, imm8) simde_undeprecated_mm_permute2_pd((a), (b), (c), (imm8)) #endif #if defined(SIMDE_X86_XOP_ENABLE_NATIVE_ALIASES) #define _mm_permute2_pd(a, b, c, imm8) simde_mm_permute2_pd((a), (b), (c), (imm8)) @@ -3589,8 +3615,21 @@ simde_mm256_permute2_ps (simde__m256 a, simde__m256 b, simde__m256i c, const int return simde__m256_from_private(r_); } + +#if defined(SIMDE_X86_XOP_NATIVE) && defined(SIMDE_BUG_PCLMUL_XOP_DEPRECATED) + SIMDE_LCC_DISABLE_DEPRECATED_WARNINGS + SIMDE_FUNCTION_ATTRIBUTES + simde__m256 + simde_undeprecated_mm256_permute2_ps (simde__m256 a, simde__m256 b, simde__m256i c, const int imm8) { + return _mm256_permute2_ps(a, b, c, imm8); + } + SIMDE_LCC_REVERT_DEPRECATED_WARNINGS +#else + #define simde_undeprecated_mm256_permute2_ps _mm256_permute2_ps +#endif + #if defined(SIMDE_X86_XOP_NATIVE) - #define simde_mm256_permute2_ps(a, b, c, imm8) _mm256_permute2_ps((a), (b), (c), (imm8)) + #define simde_mm256_permute2_ps(a, b, c, imm8) simde_undeprecated_mm256_permute2_ps((a), (b), (c), (imm8)) #endif #if defined(SIMDE_X86_XOP_ENABLE_NATIVE_ALIASES) #define _mm256_permute2_ps(a, b, c, imm8) simde_mm256_permute2_ps((a), (b), (c), (imm8)) @@ -3631,8 +3670,21 @@ simde_mm256_permute2_pd (simde__m256d a, simde__m256d b, simde__m256i c, const i return simde__m256d_from_private(r_); } + +#if defined(SIMDE_X86_XOP_NATIVE) && defined(SIMDE_BUG_PCLMUL_XOP_DEPRECATED) + SIMDE_LCC_DISABLE_DEPRECATED_WARNINGS + SIMDE_FUNCTION_ATTRIBUTES + simde__m256d + simde_undeprecated_mm256_permute2_pd (simde__m256d a, simde__m256d b, simde__m256i c, const int imm8) { + return _mm256_permute2_pd(a, b, c, imm8); + } + SIMDE_LCC_REVERT_DEPRECATED_WARNINGS +#else + #define simde_undeprecated_mm256_permute2_pd _mm256_permute2_pd +#endif + #if defined(SIMDE_X86_XOP_NATIVE) - #define simde_mm256_permute2_pd(a, b, c, imm8) _mm256_permute2_pd((a), (b), (c), (imm8)) + #define simde_mm256_permute2_pd(a, b, c, imm8) simde_undeprecated_mm256_permute2_pd((a), (b), (c), (imm8)) #endif #if defined(SIMDE_X86_XOP_ENABLE_NATIVE_ALIASES) #define _mm256_permute2_pd(a, b, c, imm8) simde_mm256_permute2_pd((a), (b), (c), (imm8)) diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt index 85fb675d6..ba62ab350 100644 --- a/test/CMakeLists.txt +++ b/test/CMakeLists.txt @@ -79,7 +79,7 @@ if("${OPENMP_SIMD_FLAGS}" STREQUAL "") check_c_compiler_flag("${omp_simd_flag}" "${omp_simd_flag_name}") if(${omp_simd_flag_name}) - set(OPENMP_SIMD_FLAGS "-DSIMDE_ENABLE_OPENMP ${omp_simd_flag}") + set(OPENMP_SIMD_FLAGS "${omp_simd_flag}") break() endif() endforeach() diff --git a/test/meson.build b/test/meson.build index 1e46dfe97..5fd453999 100644 --- a/test/meson.build +++ b/test/meson.build @@ -17,23 +17,21 @@ endif c_openmp_simd = false cxx_openmp_simd = false -# LCC has OpenMP enabled by default without any args +# LCC has OpenMP enabled by default without any args. +# For other compilers, we need to find correct one. +# We'll build tests with OpenMP SIMD enabled, if we can. if cc.get_id() == 'lcc' c_openmp_simd = true cxx_openmp_simd = true - simde_c_defs += '-DSIMDE_ENABLE_OPENMP' - simde_cxx_defs += '-DSIMDE_ENABLE_OPENMP' else foreach omp_arg : ['-fopenmp-simd', '-qopenmp-simd'] if (not c_openmp_simd) and cc.has_argument(omp_arg) simde_c_args += omp_arg - simde_c_defs += '-DSIMDE_ENABLE_OPENMP' c_openmp_simd = true endif if (not cxx_openmp_simd) and cxx.has_argument(omp_arg) simde_cxx_args += omp_arg - simde_cxx_defs += '-DSIMDE_ENABLE_OPENMP' cxx_openmp_simd = true endif endforeach @@ -67,6 +65,8 @@ if cxx.get_id() == 'intel' simde_native_cxx_flags += '-DSIMDE_FAST_MATH' endif +# If we can't use OpenMP SIMD, use OpenMP library instead, +# if available if not c_openmp_simd simde_deps += dependency('openmp', required: false) endif @@ -77,9 +77,4 @@ simde_include_dir = include_directories('..') subdir('common') subdir('x86') - -# Currently it is nearly impossible to support non-native ARM on elbrus. -# It's compiler bug, so it will be possible in future versions. -if cc.get_id() != 'lcc' - subdir('arm') -endif +subdir('arm') diff --git a/test/x86/avx.c b/test/x86/avx.c index 785861779..70712a94c 100644 --- a/test/x86/avx.c +++ b/test/x86/avx.c @@ -336,7 +336,7 @@ test_simde_mm256_set1_epi8(SIMDE_MUNIT_TEST_ARGS) { const struct { int8_t a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { 41, simde_mm256_set_epi8(INT8_C( 41), INT8_C( 41), INT8_C( 41), INT8_C( 41), INT8_C( 41), INT8_C( 41), INT8_C( 41), INT8_C( 41), @@ -424,7 +424,7 @@ test_simde_mm256_set1_epi16(SIMDE_MUNIT_TEST_ARGS) { const struct { int16_t a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { INT16_C( -7117), simde_mm256_set_epi16(INT16_C( -7117), INT16_C( -7117), INT16_C( -7117), INT16_C( -7117), INT16_C( -7117), INT16_C( -7117), INT16_C( -7117), INT16_C( -7117), @@ -480,7 +480,7 @@ test_simde_mm256_set1_epi32(SIMDE_MUNIT_TEST_ARGS) { const struct { int32_t a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { INT32_C( 1458307866), simde_mm256_set_epi32(INT32_C( 1458307866), INT32_C( 1458307866), INT32_C( 1458307866), INT32_C( 1458307866), INT32_C( 1458307866), INT32_C( 1458307866), INT32_C( 1458307866), INT32_C( 1458307866)) }, @@ -520,7 +520,7 @@ test_simde_mm256_set1_epi64x(SIMDE_MUNIT_TEST_ARGS) { const struct { int64_t a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { INT64_C( 5105791061004147197), simde_mm256_set_epi64x(INT64_C( 5105791061004147197), INT64_C( 5105791061004147197), INT64_C( 5105791061004147197), INT64_C( 5105791061004147197)) }, @@ -560,7 +560,7 @@ test_simde_mm256_set1_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde_float32 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { SIMDE_FLOAT32_C( -73.91), simde_mm256_set_ps(SIMDE_FLOAT32_C( -73.91), SIMDE_FLOAT32_C( -73.91), SIMDE_FLOAT32_C( -73.91), SIMDE_FLOAT32_C( -73.91), @@ -616,7 +616,7 @@ test_simde_mm256_set1_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde_float64 a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { SIMDE_FLOAT64_C( -494.25), simde_mm256_set_pd(SIMDE_FLOAT64_C( -494.25), SIMDE_FLOAT64_C( -494.25), SIMDE_FLOAT64_C( -494.25), SIMDE_FLOAT64_C( -494.25)) }, @@ -1207,7 +1207,7 @@ test_simde_mm256_addsub_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 a; simde__m256 b; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( -665.97), SIMDE_FLOAT32_C( -119.17), SIMDE_FLOAT32_C( 98.44), SIMDE_FLOAT32_C( -870.79), SIMDE_FLOAT32_C( 715.06), SIMDE_FLOAT32_C( 168.23), @@ -1320,7 +1320,7 @@ test_simde_mm256_addsub_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d a; simde__m256d b; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 715.06), SIMDE_FLOAT64_C( 168.23), SIMDE_FLOAT64_C( 291.85), SIMDE_FLOAT64_C( 803.77)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -279.74), SIMDE_FLOAT64_C( 960.47), @@ -1385,7 +1385,7 @@ test_simde_mm256_and_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 a; simde__m256 b; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( -927.26), SIMDE_FLOAT32_C( -802.03), SIMDE_FLOAT32_C( -266.41), SIMDE_FLOAT32_C( -50.41), SIMDE_FLOAT32_C( -309.19), SIMDE_FLOAT32_C( -707.19), @@ -1498,7 +1498,7 @@ test_simde_mm256_and_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d a; simde__m256d b; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -309.19), SIMDE_FLOAT64_C( -707.19), SIMDE_FLOAT64_C( -220.07), SIMDE_FLOAT64_C( 127.67)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -167.84), SIMDE_FLOAT64_C( 346.85), @@ -1563,7 +1563,7 @@ test_simde_mm256_andnot_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C(-1269691626), INT32_C(-1170050076), INT32_C( -309781764), INT32_C( -576457271), INT32_C( -634907762), INT32_C( 2098123667), INT32_C( -562209537), INT32_C( 5131913)), simde_mm256_set_epi32(INT32_C( 1938996560), INT32_C( -950945230), INT32_C( 1149254280), INT32_C( 44378753), @@ -1628,7 +1628,7 @@ test_simde_mm256_andnot_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C(-8439082616481350053), INT64_C(-1591722586538286382), INT64_C( 1596940992066035921), INT64_C( 7218980746644065590)), simde_mm256_set_epi64x(INT64_C(-2889835723484335944), INT64_C( 5702037989414933855), @@ -1692,7 +1692,7 @@ test_simde_mm256_castps_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 17.89), SIMDE_FLOAT32_C( -439.16), SIMDE_FLOAT32_C( 198.42), SIMDE_FLOAT32_C( 352.58), SIMDE_FLOAT32_C( 461.89), SIMDE_FLOAT32_C( -105.28), @@ -1772,7 +1772,7 @@ test_simde_mm256_castpd_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 866.38), SIMDE_FLOAT64_C( -294.05), SIMDE_FLOAT64_C( -595.07), SIMDE_FLOAT64_C( 30.82)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 866.38), SIMDE_FLOAT64_C( -294.05), @@ -1820,7 +1820,7 @@ test_simde_mm256_castps128_ps256(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_ps(SIMDE_FLOAT32_C( 351.31), SIMDE_FLOAT32_C( 331.36), SIMDE_FLOAT32_C( 112.22), SIMDE_FLOAT32_C( -15.48)), simde_mm256_set_ps(SIMDE_FLOAT32_C( 0.00), SIMDE_FLOAT32_C( 0.00), SIMDE_FLOAT32_C( 0.00), SIMDE_FLOAT32_C( 0.00), @@ -1877,7 +1877,7 @@ test_simde_mm256_castps256_ps128(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m128 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( -556.83), SIMDE_FLOAT32_C( 534.45), SIMDE_FLOAT32_C( 421.40), SIMDE_FLOAT32_C( 932.30), SIMDE_FLOAT32_C( 169.92), SIMDE_FLOAT32_C( 399.10), @@ -1933,7 +1933,7 @@ test_simde_mm256_castps_si256(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C(-1649031696), INT32_C( 834872153), INT32_C( 230986620), INT32_C( -480324866), INT32_C( 1237553077), INT32_C( 596539913), INT32_C( -724550399), INT32_C( -685617130)), simde_mm256_set_epi32(INT32_C(-1649031696), INT32_C( 834872153), INT32_C( 230986620), INT32_C( -480324866), @@ -1981,7 +1981,7 @@ test_simde_mm256_castpd_si256(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C(-6436426043624243132), INT64_C( 2719911931068686329), INT64_C(-3355851641471628446), INT64_C(-4058286728495258453)), simde_mm256_set_epi64x(INT64_C(-6436426043624243132), INT64_C( 2719911931068686329), @@ -2029,7 +2029,7 @@ test_simde_mm256_castsi128_si256(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi32(INT32_C( 1176995756), INT32_C(-1870675232), INT32_C( 996429243), INT32_C( 550488102)), simde_mm256_set_epi32(INT32_C( 0), INT32_C( 0), INT32_C( 0), INT32_C( 0), INT32_C( 1176995756), INT32_C(-1870675232), INT32_C( 996429243), INT32_C( 550488102)) }, @@ -2070,7 +2070,7 @@ test_simde_mm256_castsi256_si128(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m128i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( 1033968789), INT32_C( 712909368), INT32_C( -15382203), INT32_C( 726776461), INT32_C( 1212968394), INT32_C( -910350077), INT32_C(-1401880553), INT32_C(-1640064659)), simde_mm_set_epi32(INT32_C( 1212968394), INT32_C( -910350077), INT32_C(-1401880553), INT32_C(-1640064659)) }, @@ -2110,7 +2110,7 @@ test_simde_mm256_castsi256_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C(-1649031696), INT32_C( 834872153), INT32_C( 230986620), INT32_C( -480324866), INT32_C( 1237553077), INT32_C( 596539913), INT32_C( -724550399), INT32_C( -685617130)), simde_mm256_set_epi32(INT32_C(-1649031696), INT32_C( 834872153), INT32_C( 230986620), INT32_C( -480324866), @@ -2158,7 +2158,7 @@ test_simde_mm256_castsi256_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C(-6436426043624243132), INT64_C( 2719911931068686329), INT64_C(-3355851641471628446), INT64_C(-4058286728495258453)), simde_mm256_set_epi64x(INT64_C(-6436426043624243132), INT64_C( 2719911931068686329), @@ -2207,7 +2207,7 @@ test_simde_mm256_blend_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 a; simde__m256 b; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 61.35), SIMDE_FLOAT32_C( 540.33), SIMDE_FLOAT32_C( -888.48), SIMDE_FLOAT32_C( 570.09), SIMDE_FLOAT32_C( 312.02), SIMDE_FLOAT32_C( -960.46), @@ -2320,7 +2320,7 @@ test_simde_mm256_blend_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d a; simde__m256d b; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 983.61), SIMDE_FLOAT64_C( -51.56), SIMDE_FLOAT64_C( 561.13), SIMDE_FLOAT64_C( -977.17)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 311.03), SIMDE_FLOAT64_C( -876.87), @@ -2386,7 +2386,7 @@ test_simde_mm256_blendv_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 b; simde__m256 mask; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( -169.19), SIMDE_FLOAT32_C( -303.51), SIMDE_FLOAT32_C( 280.62), SIMDE_FLOAT32_C( 971.56), SIMDE_FLOAT32_C( 558.62), SIMDE_FLOAT32_C( 244.31), @@ -2532,7 +2532,7 @@ test_simde_mm256_blendv_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d b; simde__m256d mask; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -587.29), SIMDE_FLOAT64_C( 745.99), SIMDE_FLOAT64_C( 660.01), SIMDE_FLOAT64_C( -72.44)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 307.98), SIMDE_FLOAT64_C( 879.25), @@ -2685,7 +2685,7 @@ test_simde_mm256_broadcast_sd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde_float64 a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { SIMDE_FLOAT64_C( 800.84), simde_mm256_set_pd(SIMDE_FLOAT64_C( 800.84), SIMDE_FLOAT64_C( 800.84), SIMDE_FLOAT64_C( 800.84), SIMDE_FLOAT64_C( 800.84)) }, @@ -2757,7 +2757,7 @@ test_simde_mm256_broadcast_ss(SIMDE_MUNIT_TEST_ARGS) { const struct { simde_float32 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { SIMDE_FLOAT32_C( -970.00), simde_mm256_set_ps(SIMDE_FLOAT32_C( -970.00), SIMDE_FLOAT32_C( -970.00), SIMDE_FLOAT32_C( -970.00), SIMDE_FLOAT32_C( -970.00), @@ -2813,7 +2813,7 @@ test_simde_mm256_castpd128_pd256(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_pd(SIMDE_FLOAT64_C( -698.37), SIMDE_FLOAT64_C( 516.77)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 0.00), SIMDE_FLOAT64_C( 0.00), SIMDE_FLOAT64_C( -698.37), SIMDE_FLOAT64_C( 516.77)) }, @@ -2854,7 +2854,7 @@ test_simde_mm256_castpd256_pd128(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m128d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -956.85), SIMDE_FLOAT64_C( 625.41), SIMDE_FLOAT64_C( 728.85), SIMDE_FLOAT64_C( 239.74)), simde_mm_set_pd(SIMDE_FLOAT64_C( 728.85), SIMDE_FLOAT64_C( 239.74)) }, @@ -2894,7 +2894,7 @@ test_simde_mm256_ceil_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -242.41), SIMDE_FLOAT64_C( -377.59), SIMDE_FLOAT64_C( 787.73), SIMDE_FLOAT64_C( 903.22)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -242.00), SIMDE_FLOAT64_C( -377.00), @@ -2942,7 +2942,7 @@ test_simde_mm256_ceil_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 719.50), SIMDE_FLOAT32_C( 423.42), SIMDE_FLOAT32_C( -325.80), SIMDE_FLOAT32_C( -7.65), SIMDE_FLOAT32_C( 549.35), SIMDE_FLOAT32_C( 88.23), @@ -5023,7 +5023,7 @@ test_simde_mm256_cvtepi32_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi32(INT32_C( 1957018358), INT32_C( 1074174472), INT32_C( 124397699), INT32_C( 1881644266)), simde_mm256_set_pd(SIMDE_FLOAT64_C(1957018358.00), SIMDE_FLOAT64_C(1074174472.00), SIMDE_FLOAT64_C(124397699.00), SIMDE_FLOAT64_C(1881644266.00)) }, @@ -5063,7 +5063,7 @@ test_simde_mm256_cvtepi32_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( -6033), INT32_C( 15813), INT32_C( 12979), INT32_C( -31712), INT32_C( 18002), INT32_C( -6019), INT32_C( -26810), INT32_C( 14091)), simde_mm256_set_ps(SIMDE_FLOAT32_C(-6033.00), SIMDE_FLOAT32_C(15813.00), @@ -5127,7 +5127,7 @@ test_simde_mm256_cvtpd_epi32(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m128i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 823.92), SIMDE_FLOAT64_C( -252.31), SIMDE_FLOAT64_C( 311.42), SIMDE_FLOAT64_C( 639.08)), simde_mm_set_epi32(INT32_C( 824), INT32_C(-252), INT32_C( 311), INT32_C( 639)) }, @@ -5167,7 +5167,7 @@ test_simde_mm256_cvtpd_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m128 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 375.90), SIMDE_FLOAT64_C( -889.76), SIMDE_FLOAT64_C( -974.31), SIMDE_FLOAT64_C( 373.58)), simde_mm_set_ps(SIMDE_FLOAT32_C( 375.90), SIMDE_FLOAT32_C( -889.76), SIMDE_FLOAT32_C( -974.31), SIMDE_FLOAT32_C( 373.58)) }, @@ -5207,7 +5207,7 @@ test_simde_mm256_cvtps_epi32(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 598.58), SIMDE_FLOAT32_C( 571.41), SIMDE_FLOAT32_C( -242.37), SIMDE_FLOAT32_C( -717.41), SIMDE_FLOAT32_C( 374.26), SIMDE_FLOAT32_C( -165.53), @@ -5271,7 +5271,7 @@ test_simde_mm256_cvtps_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128 a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_ps(SIMDE_FLOAT32_C( 846.20), SIMDE_FLOAT32_C( 685.37), SIMDE_FLOAT32_C( 660.41), SIMDE_FLOAT32_C( -309.12)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 846.20), SIMDE_FLOAT64_C( 685.37), SIMDE_FLOAT64_C( 660.41), SIMDE_FLOAT64_C( -309.12)) }, @@ -5417,7 +5417,7 @@ test_simde_mm256_cvttpd_epi32(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m128i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -175.82), SIMDE_FLOAT64_C( -91.19), SIMDE_FLOAT64_C( -855.64), SIMDE_FLOAT64_C(-1000.00)), simde_mm_set_epi32(INT32_C(-175), INT32_C( -91), INT32_C(-855), INT32_C(-1000)) }, @@ -5457,7 +5457,7 @@ test_simde_mm256_cvttps_epi32(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( -135.75), SIMDE_FLOAT32_C( 534.39), SIMDE_FLOAT32_C( -81.93), SIMDE_FLOAT32_C( -234.94), SIMDE_FLOAT32_C( -390.94), SIMDE_FLOAT32_C( -625.05), @@ -5522,7 +5522,7 @@ test_simde_mm256_div_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 a; simde__m256 b; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 675.83), SIMDE_FLOAT32_C( 732.26), SIMDE_FLOAT32_C( -4.57), SIMDE_FLOAT32_C( -168.80), SIMDE_FLOAT32_C( -520.00), SIMDE_FLOAT32_C( -692.17), @@ -5634,7 +5634,7 @@ test_simde_mm256_div_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d a; simde__m256d b; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 42.76), SIMDE_FLOAT64_C( 925.42), SIMDE_FLOAT64_C( 624.80), SIMDE_FLOAT64_C( 413.87)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -621.50), SIMDE_FLOAT64_C( -651.30), @@ -5698,7 +5698,7 @@ test_simde_mm256_floor_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 520.72), SIMDE_FLOAT32_C( 834.16), SIMDE_FLOAT32_C( -945.36), SIMDE_FLOAT32_C( -135.41), SIMDE_FLOAT32_C( 289.19), SIMDE_FLOAT32_C( 462.54), @@ -5780,7 +5780,7 @@ test_simde_mm256_extractf128_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d b; simde__m128d ra; simde__m128d rb; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 115.05), SIMDE_FLOAT64_C( 580.50), SIMDE_FLOAT64_C( 784.61), SIMDE_FLOAT64_C( 6.02)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -748.60), SIMDE_FLOAT64_C( 328.25), @@ -5848,7 +5848,7 @@ test_simde_mm256_extractf128_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 b; simde__m128 ra; simde__m128 rb; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( -982.78), SIMDE_FLOAT32_C( 936.88), SIMDE_FLOAT32_C( 412.85), SIMDE_FLOAT32_C( -941.25), SIMDE_FLOAT32_C( 131.34), SIMDE_FLOAT32_C( 565.12), @@ -5948,7 +5948,7 @@ test_simde_mm256_extractf128_si256(SIMDE_MUNIT_TEST_ARGS) { simde__m256i b; simde__m128i ra; simde__m128i rb; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( 1229394801), INT32_C( 992221618), INT32_C(-1388107406), INT32_C( 780445625), INT32_C( 1795700153), INT32_C( -297324271), INT32_C( 1549329146), INT32_C( -534963225)), simde_mm256_set_epi32(INT32_C( -867719772), INT32_C(-1804212438), INT32_C( 1849818353), INT32_C( 405560893), @@ -6014,7 +6014,7 @@ test_simde_mm256_floor_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -86.60), SIMDE_FLOAT64_C( -29.62), SIMDE_FLOAT64_C( 880.65), SIMDE_FLOAT64_C( 474.01)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -87.00), SIMDE_FLOAT64_C( -30.00), @@ -6063,7 +6063,7 @@ test_simde_mm256_hadd_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 a; simde__m256 b; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( -626.68), SIMDE_FLOAT32_C( -596.09), SIMDE_FLOAT32_C( -988.19), SIMDE_FLOAT32_C( 961.65), SIMDE_FLOAT32_C( 518.43), SIMDE_FLOAT32_C( 334.09), @@ -6176,7 +6176,7 @@ test_simde_mm256_hadd_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d a; simde__m256d b; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -436.68), SIMDE_FLOAT64_C( 480.99), SIMDE_FLOAT64_C( -278.34), SIMDE_FLOAT64_C( 588.89)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 130.14), SIMDE_FLOAT64_C( -927.67), @@ -6241,7 +6241,7 @@ test_simde_mm256_hsub_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 a; simde__m256 b; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( -183.85), SIMDE_FLOAT32_C( 905.07), SIMDE_FLOAT32_C( -962.47), SIMDE_FLOAT32_C( 739.25), SIMDE_FLOAT32_C( 13.54), SIMDE_FLOAT32_C( -172.40), @@ -6354,7 +6354,7 @@ test_simde_mm256_hsub_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d a; simde__m256d b; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -762.69), SIMDE_FLOAT64_C( 237.58), SIMDE_FLOAT64_C( 832.53), SIMDE_FLOAT64_C( -18.37)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 974.95), SIMDE_FLOAT64_C( -69.86), @@ -6419,7 +6419,7 @@ test_simde_mm256_dp_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 a; simde__m256 b; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( -505.73), SIMDE_FLOAT32_C( -137.42), SIMDE_FLOAT32_C( 17.33), SIMDE_FLOAT32_C( 756.92), SIMDE_FLOAT32_C( -935.43), SIMDE_FLOAT32_C( 966.58), @@ -6999,7 +6999,7 @@ test_simde_mm256_insertf128_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m128 b; simde__m256 ra; simde__m256 rb; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 57.86), SIMDE_FLOAT32_C( 900.49), SIMDE_FLOAT32_C( 678.15), SIMDE_FLOAT32_C( -551.43), SIMDE_FLOAT32_C( 431.88), SIMDE_FLOAT32_C( -426.33), @@ -7131,7 +7131,7 @@ test_simde_mm256_insertf128_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m128d b; simde__m256d ra; simde__m256d rb; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 500.07), SIMDE_FLOAT64_C( 24.20), SIMDE_FLOAT64_C( -264.31), SIMDE_FLOAT64_C( 584.01)), simde_mm_set_pd (SIMDE_FLOAT64_C( 431.47), SIMDE_FLOAT64_C( 318.12)), @@ -7207,7 +7207,7 @@ test_simde_mm256_insertf128_si256(SIMDE_MUNIT_TEST_ARGS) { simde__m128i b; simde__m256i ra; simde__m256i rb; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( 1732788931), INT32_C( -493919285), INT32_C( -171391193), INT32_C( 1397412103), INT32_C( -356536147), INT32_C(-1692932708), INT32_C(-1699348696), INT32_C( -647395099)), simde_mm_set_epi32 (INT32_C(-1522680411), INT32_C(-1731979321), INT32_C( 1240335413), INT32_C( 201854332)), @@ -7281,7 +7281,7 @@ test_simde_mm256_lddqu_si256(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( -208613396), INT32_C( 972060947), INT32_C( 1079690819), INT32_C(-1629141358), INT32_C( -291568998), INT32_C( -706346303), INT32_C( 1782265269), INT32_C( 663843445)), simde_mm256_set_epi32(INT32_C( -208613396), INT32_C( 972060947), INT32_C( 1079690819), INT32_C(-1629141358), @@ -7329,7 +7329,7 @@ test_simde_mm256_load_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde_float64 a[sizeof(simde__m256d) / sizeof(simde_float64)]; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { { SIMDE_FLOAT64_C( -338.67), SIMDE_FLOAT64_C( 630.84), SIMDE_FLOAT64_C( -302.19), SIMDE_FLOAT64_C( -238.77) }, simde_mm256_set_pd(SIMDE_FLOAT64_C( -238.77), SIMDE_FLOAT64_C( -302.19), SIMDE_FLOAT64_C( 630.84), SIMDE_FLOAT64_C( -338.67)) }, @@ -7369,7 +7369,7 @@ test_simde_mm256_load_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { SIMDE_ALIGN_LIKE_32(simde__m256) simde_float32 a[sizeof(simde__m256) / sizeof(simde_float32)]; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { { SIMDE_FLOAT32_C( -651.15), SIMDE_FLOAT32_C( 486.09), SIMDE_FLOAT32_C( 809.52), SIMDE_FLOAT32_C( 897.18), SIMDE_FLOAT32_C( -164.76), SIMDE_FLOAT32_C( 925.08), @@ -7449,7 +7449,7 @@ test_simde_mm256_load_si256(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( 93433077), INT32_C( 912488615), INT32_C( -849505573), INT32_C( -538760324), INT32_C( 576018808), INT32_C( 306399285), INT32_C( 761465198), INT32_C( 67322681)), simde_mm256_set_epi32(INT32_C( 93433077), INT32_C( 912488615), INT32_C( -849505573), INT32_C( -538760324), @@ -7497,7 +7497,7 @@ test_simde_mm256_loadu_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde_float64 a[sizeof(simde__m256d) / sizeof(simde_float64)]; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { { SIMDE_FLOAT64_C( -245.76), SIMDE_FLOAT64_C( -764.95), SIMDE_FLOAT64_C( 498.87), SIMDE_FLOAT64_C( -327.12) }, simde_mm256_set_pd(SIMDE_FLOAT64_C( -327.12), SIMDE_FLOAT64_C( 498.87), @@ -7545,7 +7545,7 @@ test_simde_mm256_loadu_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde_float32 a[sizeof(simde__m256) / sizeof(simde_float32)]; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { { SIMDE_FLOAT32_C( 989.38), SIMDE_FLOAT32_C( -636.59), SIMDE_FLOAT32_C( 969.19), SIMDE_FLOAT32_C( 802.78), SIMDE_FLOAT32_C( -677.79), SIMDE_FLOAT32_C( 669.00), @@ -7625,7 +7625,7 @@ test_simde_mm256_loadu_si256(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( 93433077), INT32_C( 912488615), INT32_C( -849505573), INT32_C( -538760324), INT32_C( 576018808), INT32_C( 306399285), INT32_C( 761465198), INT32_C( 67322681)), simde_mm256_set_epi32(INT32_C( 93433077), INT32_C( 912488615), INT32_C( -849505573), INT32_C( -538760324), @@ -7674,7 +7674,7 @@ test_simde_mm256_loadu2_m128(SIMDE_MUNIT_TEST_ARGS) { simde_float32 a[sizeof(simde__m128) / sizeof(simde_float32)]; simde_float32 b[sizeof(simde__m128) / sizeof(simde_float32)]; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { { SIMDE_FLOAT32_C( 13.39), SIMDE_FLOAT32_C( 253.33), SIMDE_FLOAT32_C( 769.78), SIMDE_FLOAT32_C( 607.23) }, { SIMDE_FLOAT32_C( 382.59), SIMDE_FLOAT32_C( 295.37), SIMDE_FLOAT32_C( -847.51), SIMDE_FLOAT32_C( -193.22) }, simde_mm256_set_ps(SIMDE_FLOAT32_C( 607.23), SIMDE_FLOAT32_C( 769.78), @@ -7739,7 +7739,7 @@ test_simde_mm256_loadu2_m128d(SIMDE_MUNIT_TEST_ARGS) { simde_float64 a[sizeof(simde__m128d) / sizeof(simde_float64)]; simde_float64 b[sizeof(simde__m128d) / sizeof(simde_float64)]; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { { SIMDE_FLOAT64_C( 193.14), SIMDE_FLOAT64_C( -237.27) }, { SIMDE_FLOAT64_C( 826.89), SIMDE_FLOAT64_C( -516.49) }, simde_mm256_set_pd(SIMDE_FLOAT64_C( -237.27), SIMDE_FLOAT64_C( 193.14), @@ -7788,7 +7788,7 @@ test_simde_mm256_loadu2_m128i(SIMDE_MUNIT_TEST_ARGS) { simde__m128i a; simde__m128i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi32(INT32_C( 354008351), INT32_C( 1710178598), INT32_C( 1223789711), INT32_C(-1500329554)), simde_mm_set_epi32(INT32_C(-1388022686), INT32_C( -390861004), INT32_C( -560834160), INT32_C( 1618430517)), simde_mm256_set_epi32(INT32_C( 354008351), INT32_C( 1710178598), INT32_C( 1223789711), INT32_C(-1500329554), @@ -8074,7 +8074,7 @@ test_simde_mm256_maskstore_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256i mask; simde_float64 ri[4]; simde_float64 ro[4]; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 256.10), SIMDE_FLOAT64_C( 343.75), SIMDE_FLOAT64_C( -441.90), SIMDE_FLOAT64_C( 609.80)), simde_mm256_set_epi64x(INT64_C( 4260458650207424972), INT64_C( 7445494124920454187), @@ -8210,7 +8210,7 @@ test_simde_mm256_maskstore_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256i mask; simde_float32 ri[8]; simde_float32 ro[8]; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 631.62), SIMDE_FLOAT32_C( -891.94), SIMDE_FLOAT32_C( -689.27), SIMDE_FLOAT32_C( 347.81), SIMDE_FLOAT32_C( -616.22), SIMDE_FLOAT32_C( 642.58), @@ -8341,7 +8341,7 @@ test_simde_mm256_min_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 a; simde__m256 b; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 620.32), SIMDE_FLOAT32_C( -596.35), SIMDE_FLOAT32_C( 174.72), SIMDE_FLOAT32_C( 165.53), SIMDE_FLOAT32_C( 242.92), SIMDE_FLOAT32_C( 330.00), @@ -8454,7 +8454,7 @@ test_simde_mm256_min_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d a; simde__m256d b; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 207.41), SIMDE_FLOAT64_C( 328.63), SIMDE_FLOAT64_C( -694.69), SIMDE_FLOAT64_C( 687.63)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 89.05), SIMDE_FLOAT64_C( 448.86), @@ -8519,7 +8519,7 @@ test_simde_mm256_max_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 a; simde__m256 b; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 449.92), SIMDE_FLOAT32_C( 34.28), SIMDE_FLOAT32_C( -25.78), SIMDE_FLOAT32_C( 210.08), SIMDE_FLOAT32_C( 389.04), SIMDE_FLOAT32_C( -871.84), @@ -8632,7 +8632,7 @@ test_simde_mm256_max_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d a; simde__m256d b; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -66.36), SIMDE_FLOAT64_C( -982.48), SIMDE_FLOAT64_C( -994.10), SIMDE_FLOAT64_C( 656.44)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 58.12), SIMDE_FLOAT64_C( 730.28), @@ -8696,7 +8696,7 @@ test_simde_mm256_movedup_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -848.53), SIMDE_FLOAT64_C( -411.84), SIMDE_FLOAT64_C( -162.95), SIMDE_FLOAT64_C( 899.65)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -411.84), SIMDE_FLOAT64_C( -411.84), @@ -8744,7 +8744,7 @@ test_simde_mm256_movehdup_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 948.05), SIMDE_FLOAT32_C( -208.59), SIMDE_FLOAT32_C( -422.71), SIMDE_FLOAT32_C( -254.03), SIMDE_FLOAT32_C( 4.80), SIMDE_FLOAT32_C( -671.71), @@ -8824,7 +8824,7 @@ test_simde_mm256_moveldup_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 366.49), SIMDE_FLOAT32_C( -15.43), SIMDE_FLOAT32_C( -732.71), SIMDE_FLOAT32_C( 312.44), SIMDE_FLOAT32_C( -535.64), SIMDE_FLOAT32_C( -24.14), @@ -8904,7 +8904,7 @@ test_simde_mm256_movemask_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; int r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C(-1882468747), INT32_C( 687119108), INT32_C( 990615051), INT32_C(-1253009356), INT32_C( -617641993), INT32_C(-1788847115), INT32_C( 1286496634), INT32_C( -717001088)), 157 }, @@ -8944,7 +8944,7 @@ test_simde_mm256_movemask_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; int r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C(-3476114617639449125), INT64_C( 4174348817044283167), INT64_C( 2372823762134739460), INT64_C( 2922754125044459603)), 8 }, @@ -8985,7 +8985,7 @@ test_simde_mm256_mul_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 a; simde__m256 b; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( -65.11), SIMDE_FLOAT32_C( 729.63), SIMDE_FLOAT32_C( 579.86), SIMDE_FLOAT32_C( 759.34), SIMDE_FLOAT32_C( 638.63), SIMDE_FLOAT32_C( 366.71), @@ -9098,7 +9098,7 @@ test_simde_mm256_mul_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d a; simde__m256d b; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -216.07), SIMDE_FLOAT64_C( -759.70), SIMDE_FLOAT64_C( -257.81), SIMDE_FLOAT64_C( 916.82)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -279.71), SIMDE_FLOAT64_C( 654.36), @@ -9163,7 +9163,7 @@ test_simde_mm256_or_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 a; simde__m256 b; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( -856.34), SIMDE_FLOAT32_C( -251.54), SIMDE_FLOAT32_C( 873.84), SIMDE_FLOAT32_C( 282.56), SIMDE_FLOAT32_C( -701.43), SIMDE_FLOAT32_C( 881.08), @@ -9276,7 +9276,7 @@ test_simde_mm256_or_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( -465239073), INT32_C( 1279184195), INT32_C( 2016764339), INT32_C(-2145324536), INT32_C(-1764212445), INT32_C( 366604460), INT32_C( 2076865232), INT32_C( -193563958)), simde_mm256_set_epi32(INT32_C( 541400396), INT32_C( -972933189), INT32_C( 510962050), INT32_C( -823731197), @@ -9341,7 +9341,7 @@ test_simde_mm256_permute_ps(SIMDE_MUNIT_TEST_ARGS) { struct { simde__m256 a; simde__m256 r; - } p[8]; + } SIMDE_ALIGN_REDUCE_STRUCT p[8]; } test_vec[1] = { { { @@ -9635,7 +9635,7 @@ test_simde_mm256_permute_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a[4]; simde__m256d r[4]; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -307.33), SIMDE_FLOAT64_C( -277.83), SIMDE_FLOAT64_C( -811.26), SIMDE_FLOAT64_C( -340.98)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 520.01), SIMDE_FLOAT64_C( 20.96), @@ -9873,7 +9873,7 @@ test_simde_mm256_permutevar_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 a; simde__m256i b; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( -581.11), SIMDE_FLOAT32_C( 662.67), SIMDE_FLOAT32_C( 749.10), SIMDE_FLOAT32_C( 794.46), SIMDE_FLOAT32_C( 351.98), SIMDE_FLOAT32_C( 95.47), @@ -9970,7 +9970,7 @@ test_simde_mm256_permutevar_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d a; simde__m256i b; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 191.45), SIMDE_FLOAT64_C( 955.97), SIMDE_FLOAT64_C( -381.93), SIMDE_FLOAT64_C( -276.35)), simde_mm256_set_epi64x(INT64_C( 7847047898918917938), INT64_C(-2237739371695600451), @@ -10035,7 +10035,7 @@ test_simde_mm256_permute2f128_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 a; simde__m256 b; simde__m256 r; - } test_vec[] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( -376.93), SIMDE_FLOAT32_C( -598.80), SIMDE_FLOAT32_C( 335.44), SIMDE_FLOAT32_C( -614.52), SIMDE_FLOAT32_C( 219.29), SIMDE_FLOAT32_C( -425.58), @@ -10288,7 +10288,7 @@ test_simde_mm256_rcp_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( -908.92), SIMDE_FLOAT32_C( -201.59), SIMDE_FLOAT32_C( 3.47), SIMDE_FLOAT32_C( 829.08), SIMDE_FLOAT32_C( -86.36), SIMDE_FLOAT32_C( 780.02), @@ -10371,7 +10371,7 @@ test_simde_mm256_round_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 neg_inf; simde__m256 pos_inf; simde__m256 truncate; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( -437.99), SIMDE_FLOAT32_C( 332.86), SIMDE_FLOAT32_C( 531.55), SIMDE_FLOAT32_C( 188.24), SIMDE_FLOAT32_C( 135.31), SIMDE_FLOAT32_C( -341.69), @@ -10561,7 +10561,7 @@ test_simde_mm256_round_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d neg_inf; simde__m256d pos_inf; simde__m256d truncate; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 312.12), SIMDE_FLOAT64_C( 818.22), SIMDE_FLOAT64_C( 62.47), SIMDE_FLOAT64_C( 918.37)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 312.00), SIMDE_FLOAT64_C( 818.00), @@ -10668,7 +10668,7 @@ test_simde_mm256_rsqrt_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 376.34), SIMDE_FLOAT32_C( 781.09), SIMDE_FLOAT32_C( 426.92), SIMDE_FLOAT32_C( 127.71), SIMDE_FLOAT32_C( 308.06), SIMDE_FLOAT32_C( 169.26), @@ -10748,7 +10748,7 @@ test_simde_mm256_setr_epi8(SIMDE_MUNIT_TEST_ARGS) { const struct { int8_t a[32]; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { { INT8_C( -4), INT8_C( 97), INT8_C( -85), INT8_C( -82), INT8_C( 42), INT8_C( 35), INT8_C( 11), INT8_C( 62), INT8_C( -47), INT8_C( 10), INT8_C(-127), INT8_C( 56), @@ -10900,7 +10900,7 @@ test_simde_mm256_setr_epi16(SIMDE_MUNIT_TEST_ARGS) { const struct { int16_t a[16]; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { { INT16_C(-20822), INT16_C( 4719), INT16_C( 13700), INT16_C( 26280), INT16_C( -8393), INT16_C( 13684), INT16_C(-27950), INT16_C(-18508), INT16_C( 32037), INT16_C(-24299), INT16_C(-21546), INT16_C( 1669), @@ -10984,7 +10984,7 @@ test_simde_mm256_setr_epi32(SIMDE_MUNIT_TEST_ARGS) { const struct { int32_t a[8]; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { { INT32_C( 932849909), INT32_C( -456580424), INT32_C(-1072840342), INT32_C( 187025165), INT32_C( -54386372), INT32_C(-1527557226), INT32_C( 842765893), INT32_C(-1371730077) }, simde_mm256_set_epi32(INT32_C(-1371730077), INT32_C( 842765893), INT32_C(-1527557226), INT32_C( -54386372), @@ -11034,7 +11034,7 @@ test_simde_mm256_setr_epi64x(SIMDE_MUNIT_TEST_ARGS) { const struct { int64_t a[4]; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { { INT64_C( 3013620110861784505), INT64_C(-9156069624919168580), INT64_C( 1343723656449999612), INT64_C(-3830101585267880776) }, simde_mm256_set_epi64x(INT64_C(-3830101585267880776), INT64_C( 1343723656449999612), @@ -11083,7 +11083,7 @@ test_simde_mm256_setr_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde_float32 a[8]; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { { SIMDE_FLOAT32_C( -98.84), SIMDE_FLOAT32_C( 882.16), SIMDE_FLOAT32_C( 306.69), SIMDE_FLOAT32_C( -539.67), SIMDE_FLOAT32_C( -947.14), SIMDE_FLOAT32_C( -871.17), @@ -11165,7 +11165,7 @@ test_simde_mm256_setr_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde_float64 a[4]; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { { SIMDE_FLOAT64_C( 648.06), SIMDE_FLOAT64_C( -427.64), SIMDE_FLOAT64_C( 870.51), SIMDE_FLOAT64_C( -400.08) }, simde_mm256_set_pd(SIMDE_FLOAT64_C( -400.08), SIMDE_FLOAT64_C( 870.51), @@ -11215,7 +11215,7 @@ test_simde_mm256_setr_m128(SIMDE_MUNIT_TEST_ARGS) { simde__m128 a; simde__m128 b; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_ps(SIMDE_FLOAT32_C( -682.25), SIMDE_FLOAT32_C( -899.79), SIMDE_FLOAT32_C( -478.94), SIMDE_FLOAT32_C( 364.00)), simde_mm_set_ps(SIMDE_FLOAT32_C( -650.11), SIMDE_FLOAT32_C( -192.16), SIMDE_FLOAT32_C( 808.30), SIMDE_FLOAT32_C( 519.14)), simde_mm256_set_ps(SIMDE_FLOAT32_C( -650.11), SIMDE_FLOAT32_C( -192.16), @@ -11280,7 +11280,7 @@ test_simde_mm256_setr_m128d(SIMDE_MUNIT_TEST_ARGS) { simde__m128d a; simde__m128d b; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_pd(SIMDE_FLOAT64_C( -456.75), SIMDE_FLOAT64_C( -671.00)), simde_mm_set_pd(SIMDE_FLOAT64_C( -831.34), SIMDE_FLOAT64_C( 280.05)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -831.34), SIMDE_FLOAT64_C( 280.05), @@ -11329,7 +11329,7 @@ test_simde_mm256_setr_m128i(SIMDE_MUNIT_TEST_ARGS) { simde__m128i a; simde__m128i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi32(INT32_C(-1742712724), INT32_C( -314784100), INT32_C( 986737210), INT32_C( 1275380805)), simde_mm_set_epi32(INT32_C( -652328462), INT32_C(-1178876865), INT32_C(-2116026355), INT32_C( 283851183)), simde_mm256_set_epi32(INT32_C( -652328462), INT32_C(-1178876865), INT32_C(-2116026355), INT32_C( 283851183), @@ -11379,7 +11379,7 @@ test_simde_mm256_shuffle_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 b; simde__m256 r1; simde__m256 r2; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( -37.53), SIMDE_FLOAT32_C( 505.45), SIMDE_FLOAT32_C( -772.05), SIMDE_FLOAT32_C( -524.38), SIMDE_FLOAT32_C( 32.28), SIMDE_FLOAT32_C( 575.28), @@ -11530,7 +11530,7 @@ test_simde_mm256_shuffle_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d b; simde__m256d r1; simde__m256d r2; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 934.66), SIMDE_FLOAT64_C( -881.67), SIMDE_FLOAT64_C( 836.94), SIMDE_FLOAT64_C( -777.20)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -249.31), SIMDE_FLOAT64_C( 364.30), @@ -11615,7 +11615,7 @@ test_simde_mm256_sqrt_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 37.27), SIMDE_FLOAT32_C( 842.37), SIMDE_FLOAT32_C( 821.35), SIMDE_FLOAT32_C( 882.42), SIMDE_FLOAT32_C( 506.85), SIMDE_FLOAT32_C( 418.78), @@ -11733,7 +11733,7 @@ test_simde_mm256_sqrt_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 121.95), SIMDE_FLOAT64_C( 169.21), SIMDE_FLOAT64_C( 224.34), SIMDE_FLOAT64_C( 661.75)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 11.04), SIMDE_FLOAT64_C( 13.01), @@ -11781,7 +11781,7 @@ test_simde_mm256_store_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; SIMDE_ALIGN_LIKE_32(simde__m256) simde_float32 r[8]; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 256.09), SIMDE_FLOAT32_C( 768.79), SIMDE_FLOAT32_C( 201.90), SIMDE_FLOAT32_C( 339.33), SIMDE_FLOAT32_C( 957.46), SIMDE_FLOAT32_C( 728.44), @@ -11862,7 +11862,7 @@ test_simde_mm256_store_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; SIMDE_ALIGN_LIKE_32(simde__m256d) simde_float64 r[4]; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 771.84), SIMDE_FLOAT64_C( 578.19), SIMDE_FLOAT64_C( 287.63), SIMDE_FLOAT64_C( 196.16)), { SIMDE_FLOAT64_C( 196.16), SIMDE_FLOAT64_C( 287.63), @@ -11911,7 +11911,7 @@ test_simde_mm256_store_si256(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( -495387953), INT32_C( 1389422093), INT32_C( 1549613541), INT32_C( 1621396930), INT32_C( 431885981), INT32_C( -495493978), INT32_C( 957980176), INT32_C( -756622382)), simde_mm256_set_epi32(INT32_C( -495387953), INT32_C( 1389422093), INT32_C( 1549613541), INT32_C( 1621396930), @@ -11960,7 +11960,7 @@ test_simde_mm256_storeu_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde_float32 r[8]; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 389.47), SIMDE_FLOAT32_C( -23.53), SIMDE_FLOAT32_C( 971.41), SIMDE_FLOAT32_C( 968.93), SIMDE_FLOAT32_C( 388.52), SIMDE_FLOAT32_C( 400.32), @@ -12041,7 +12041,7 @@ test_simde_mm256_storeu_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde_float64 r[4]; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -416.91), SIMDE_FLOAT64_C( -266.91), SIMDE_FLOAT64_C( 400.77), SIMDE_FLOAT64_C( 614.06)), { SIMDE_FLOAT64_C( 614.06), SIMDE_FLOAT64_C( 400.77), @@ -12090,7 +12090,7 @@ test_simde_mm256_storeu_si256(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C(-1690076372), INT32_C( 273159718), INT32_C( 661600261), INT32_C( -431509063), INT32_C(-1410315245), INT32_C( 938478074), INT32_C( -325173074), INT32_C( -955068873)), simde_mm256_set_epi32(INT32_C(-1690076372), INT32_C( 273159718), INT32_C( 661600261), INT32_C( -431509063), @@ -12140,7 +12140,7 @@ test_simde_mm256_storeu2_m128d(SIMDE_MUNIT_TEST_ARGS) { simde__m256d a; simde_float64 lo[2]; simde_float64 hi[2]; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -194.98), SIMDE_FLOAT64_C( 916.70), SIMDE_FLOAT64_C( 887.89), SIMDE_FLOAT64_C( -369.82)), { SIMDE_FLOAT64_C( -369.82), SIMDE_FLOAT64_C( 887.89) }, @@ -12192,7 +12192,7 @@ test_simde_mm256_storeu2_m128(SIMDE_MUNIT_TEST_ARGS) { simde__m256 a; simde_float32 lo[4]; simde_float32 hi[4]; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 443.79), SIMDE_FLOAT32_C( -943.66), SIMDE_FLOAT32_C( -617.03), SIMDE_FLOAT32_C( 623.90), SIMDE_FLOAT32_C( 762.13), SIMDE_FLOAT32_C( -191.81), @@ -12276,7 +12276,7 @@ test_simde_mm256_storeu2_m128i(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m128i lo; simde__m128i hi; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( 393618896), INT32_C(-2001591323), INT32_C( 571243540), INT32_C( -991131551), INT32_C(-1628428871), INT32_C(-1785170070), INT32_C(-1344585991), INT32_C( 394549136)), simde_mm_set_epi32(INT32_C(-1628428871), INT32_C(-1785170070), INT32_C(-1344585991), INT32_C( 394549136)), @@ -12326,7 +12326,7 @@ test_simde_mm256_stream_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; SIMDE_ALIGN_LIKE_32(simde__m256) simde_float32 r[8]; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 256.09), SIMDE_FLOAT32_C( 768.79), SIMDE_FLOAT32_C( 201.90), SIMDE_FLOAT32_C( 339.33), SIMDE_FLOAT32_C( 957.46), SIMDE_FLOAT32_C( 728.44), @@ -12407,7 +12407,7 @@ test_simde_mm256_stream_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; SIMDE_ALIGN_LIKE_32(simde__m256d) simde_float64 r[4]; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 771.84), SIMDE_FLOAT64_C( 578.19), SIMDE_FLOAT64_C( 287.63), SIMDE_FLOAT64_C( 196.16)), { SIMDE_FLOAT64_C( 196.16), SIMDE_FLOAT64_C( 287.63), @@ -12456,7 +12456,7 @@ test_simde_mm256_stream_si256(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( -495387953), INT32_C( 1389422093), INT32_C( 1549613541), INT32_C( 1621396930), INT32_C( 431885981), INT32_C( -495493978), INT32_C( 957980176), INT32_C( -756622382)), simde_mm256_set_epi32(INT32_C( -495387953), INT32_C( 1389422093), INT32_C( 1549613541), INT32_C( 1621396930), @@ -12506,7 +12506,7 @@ test_simde_mm256_sub_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 a; simde__m256 b; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 895.54), SIMDE_FLOAT32_C( -418.39), SIMDE_FLOAT32_C( -695.61), SIMDE_FLOAT32_C( -703.30), SIMDE_FLOAT32_C( -607.73), SIMDE_FLOAT32_C( 485.65), @@ -12619,7 +12619,7 @@ test_simde_mm256_sub_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d a; simde__m256d b; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -472.29), SIMDE_FLOAT64_C( 818.19), SIMDE_FLOAT64_C( -310.33), SIMDE_FLOAT64_C( -307.48)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 349.11), SIMDE_FLOAT64_C( 984.47), @@ -12722,7 +12722,7 @@ test_simde_mm256_unpackhi_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 a; simde__m256 b; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 807.72), SIMDE_FLOAT32_C( 100.14), SIMDE_FLOAT32_C( 187.05), SIMDE_FLOAT32_C( -298.31), SIMDE_FLOAT32_C( -34.37), SIMDE_FLOAT32_C( 964.34), @@ -12835,7 +12835,7 @@ test_simde_mm256_unpackhi_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d a; simde__m256d b; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 474.20), SIMDE_FLOAT64_C( -84.92), SIMDE_FLOAT64_C( 521.98), SIMDE_FLOAT64_C( -506.09)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 547.06), SIMDE_FLOAT64_C( -105.08), @@ -12900,7 +12900,7 @@ test_simde_mm256_unpacklo_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 a; simde__m256 b; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 476.45), SIMDE_FLOAT32_C( 703.11), SIMDE_FLOAT32_C( 221.80), SIMDE_FLOAT32_C( -361.45), SIMDE_FLOAT32_C( 645.73), SIMDE_FLOAT32_C( 420.76), @@ -13013,7 +13013,7 @@ test_simde_mm256_unpacklo_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d a; simde__m256d b; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -600.90), SIMDE_FLOAT64_C( -534.18), SIMDE_FLOAT64_C( -294.96), SIMDE_FLOAT64_C( 194.68)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 653.08), SIMDE_FLOAT64_C( -555.28), @@ -13078,7 +13078,7 @@ test_simde_mm256_xor_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d a; simde__m256d b; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 125.09), SIMDE_FLOAT64_C( 533.33), SIMDE_FLOAT64_C( 190.03), SIMDE_FLOAT64_C( -352.74)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 208.67), SIMDE_FLOAT64_C( -937.37), @@ -13143,7 +13143,7 @@ test_simde_mm256_xor_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 a; simde__m256 b; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 548.70), SIMDE_FLOAT32_C( -868.78), SIMDE_FLOAT32_C( -8.43), SIMDE_FLOAT32_C( -89.68), SIMDE_FLOAT32_C( -222.56), SIMDE_FLOAT32_C( 837.57), @@ -13256,7 +13256,7 @@ test_simde_mm256_zextps128_ps256(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_ps(SIMDE_FLOAT32_C( -312.77), SIMDE_FLOAT32_C( 594.20), SIMDE_FLOAT32_C( -325.59), SIMDE_FLOAT32_C( -490.02)), simde_mm256_set_ps(SIMDE_FLOAT32_C( 0.00), SIMDE_FLOAT32_C( 0.00), @@ -13320,7 +13320,7 @@ test_simde_mm256_zextpd128_pd256(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_pd(SIMDE_FLOAT64_C( 376.29), SIMDE_FLOAT64_C( -625.09)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 0.00), SIMDE_FLOAT64_C( 0.00), SIMDE_FLOAT64_C( 376.29), SIMDE_FLOAT64_C( -625.09)) }, @@ -13475,7 +13475,7 @@ test_simde_mm256_testc_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 a; simde__m256 b; int r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( -169.00), SIMDE_FLOAT32_C( -295.41), SIMDE_FLOAT32_C( 260.09), SIMDE_FLOAT32_C( -617.68), SIMDE_FLOAT32_C( 318.47), SIMDE_FLOAT32_C( -889.00), @@ -13564,7 +13564,7 @@ test_simde_mm256_testc_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d a; simde__m256d b; int r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 123.47), SIMDE_FLOAT64_C( 212.54), SIMDE_FLOAT64_C( 522.75), SIMDE_FLOAT64_C( 1.15)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -709.99), SIMDE_FLOAT64_C( 514.03), @@ -13621,7 +13621,7 @@ test_simde_mm256_testc_si256(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; int r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( 1590541233), INT32_C( -436989526), INT32_C(-1581572624), INT32_C(-1048507105), INT32_C(-1251227046), INT32_C( -111355701), INT32_C( 463981150), INT32_C(-1310282310)), simde_mm256_set_epi32(INT32_C(-1730174443), INT32_C( 962749992), INT32_C( 1889650969), INT32_C(-1644227432), @@ -13760,7 +13760,7 @@ test_simde_mm256_testz_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 a; simde__m256 b; int r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 203.89), SIMDE_FLOAT32_C( 929.87), SIMDE_FLOAT32_C( -921.04), SIMDE_FLOAT32_C( -927.33), SIMDE_FLOAT32_C( 876.23), SIMDE_FLOAT32_C( 583.50), @@ -13849,7 +13849,7 @@ test_simde_mm256_testz_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d a; simde__m256d b; int r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 374.19), SIMDE_FLOAT64_C( -934.66), SIMDE_FLOAT64_C( 991.69), SIMDE_FLOAT64_C( 768.86)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 772.38), SIMDE_FLOAT64_C( 118.89), @@ -13906,7 +13906,7 @@ test_simde_mm256_testz_si256(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; int r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C( 6293711937966483210), INT64_C( 1880458700636896550), INT64_C(-2395812271494697349), INT64_C(-3219984426865676065)), simde_mm256_set_epi64x(INT64_C(-5944145716236985819), INT64_C( 3393778583556144207), @@ -14045,7 +14045,7 @@ test_simde_mm256_testnzc_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 a; simde__m256 b; int r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 583.89), SIMDE_FLOAT32_C( -712.24), SIMDE_FLOAT32_C( -125.89), SIMDE_FLOAT32_C( 188.79), SIMDE_FLOAT32_C( 520.73), SIMDE_FLOAT32_C( -68.12), @@ -14134,7 +14134,7 @@ test_simde_mm256_testnzc_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d a; simde__m256d b; int r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -740.05), SIMDE_FLOAT64_C( -803.89), SIMDE_FLOAT64_C( -738.69), SIMDE_FLOAT64_C( -907.97)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -601.20), SIMDE_FLOAT64_C( 873.56), @@ -14191,7 +14191,7 @@ test_simde_mm256_testnzc_si256(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; int r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C(-6804708873655136040), INT64_C( 4446918229480945172), INT64_C(-6458803806102185271), INT64_C( 6419639704555297719)), simde_mm256_set_epi64x(INT64_C( 4086527184939990173), INT64_C(-4592254743728630867), diff --git a/test/x86/avx2.c b/test/x86/avx2.c index 7beff5b45..4bc7ac47c 100644 --- a/test/x86/avx2.c +++ b/test/x86/avx2.c @@ -30,7 +30,7 @@ test_simde_mm256_abs_epi8(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C( -27), INT8_C( 88), INT8_C(-122), INT8_C( -6), INT8_C( -23), INT8_C( 108), INT8_C(-103), INT8_C( 32), INT8_C( 43), INT8_C( 116), INT8_C( -6), INT8_C( -98), @@ -174,7 +174,7 @@ test_simde_mm256_abs_epi16(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi16(INT16_C( 9101), INT16_C( 13664), INT16_C( 14007), INT16_C( 17440), INT16_C( 21201), INT16_C(-16892), INT16_C(-22702), INT16_C(-11875), INT16_C( 9352), INT16_C( 21001), INT16_C( 15464), INT16_C( 27994), @@ -254,7 +254,7 @@ test_simde_mm256_abs_epi32(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( 596456800), INT32_C( 917980192), INT32_C( 1389477380), INT32_C(-1487744611), INT32_C( 612913673), INT32_C( 1013476698), INT32_C( 793290876), INT32_C(-1404571583)), simde_mm256_set_epi32(INT32_C( 596456800), INT32_C( 917980192), INT32_C( 1389477380), INT32_C( 1487744611), @@ -572,7 +572,7 @@ test_simde_mm256_alignr_epi8_case0(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C( 57), INT8_C( -47), INT8_C( -81), INT8_C( -95), INT8_C(-100), INT8_C( -69), INT8_C( -75), INT8_C(-127), INT8_C( -8), INT8_C( -83), INT8_C( -94), INT8_C(-113), @@ -781,7 +781,7 @@ test_simde_mm256_alignr_epi8_case1(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C( 57), INT8_C( -47), INT8_C( -81), INT8_C( -95), INT8_C(-100), INT8_C( -69), INT8_C( -75), INT8_C(-127), INT8_C( -8), INT8_C( -83), INT8_C( -94), INT8_C(-113), @@ -990,7 +990,7 @@ test_simde_mm256_alignr_epi8_case2(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C( 113), INT8_C( -69), INT8_C( 23), INT8_C( -66), INT8_C( 115), INT8_C( -83), INT8_C( -66), INT8_C( -71), INT8_C( 28), INT8_C( 74), INT8_C( -4), INT8_C( 16), @@ -1199,7 +1199,7 @@ test_simde_mm256_alignr_epi8_case3(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C( 57), INT8_C( -47), INT8_C( -81), INT8_C( -95), INT8_C(-100), INT8_C( -69), INT8_C( -75), INT8_C(-127), INT8_C( -8), INT8_C( -83), INT8_C( -94), INT8_C(-113), @@ -1408,7 +1408,7 @@ test_simde_mm256_and_si256(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C( 8722470578646828517), INT64_C( 891261850847437783), INT64_C( 8698554819020653857), INT64_C(-7282900013878242954)), simde_mm256_set_epi64x(INT64_C(-8128142018056442141), INT64_C( 5559182722028422309), @@ -1473,7 +1473,7 @@ test_simde_mm256_andnot_si256(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( 1296069903), INT32_C( -401713319), INT32_C( -398512257), INT32_C( 1831595067), INT32_C( -79935516), INT32_C(-1180021826), INT32_C( 1322035843), INT32_C( 1532358492)), simde_mm256_set_epi32(INT32_C( 1994603249), INT32_C(-1155877896), INT32_C( 1480474617), INT32_C( 1055447888), @@ -1538,7 +1538,7 @@ test_simde_mm256_adds_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C(-119), INT8_C( -56), INT8_C( 53), INT8_C(-117), INT8_C( 25), INT8_C( -8), INT8_C( -23), INT8_C( -22), INT8_C( 105), INT8_C( 21), INT8_C( -22), INT8_C(-123), @@ -1747,7 +1747,7 @@ test_simde_mm256_adds_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi16(INT16_C( -962), INT16_C( 12004), INT16_C( 15276), INT16_C( 19344), INT16_C( 1682), INT16_C( 24393), INT16_C(-26791), INT16_C( 15115), INT16_C( 26019), INT16_C(-25175), INT16_C(-17857), INT16_C( 29245), @@ -1860,7 +1860,7 @@ test_simde_mm256_adds_epu8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm256_set_epu8(UINT8_C(253), UINT8_C(134), UINT8_C(240), UINT8_C(121), UINT8_C(194), UINT8_C( 6), UINT8_C( 90), UINT8_C(185), UINT8_C( 52), UINT8_C(188), UINT8_C(255), UINT8_C(213), @@ -2069,7 +2069,7 @@ test_simde_mm256_adds_epu16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm256_set_epu16(UINT16_C( 46173), UINT16_C( 51502), UINT16_C( 53334), UINT16_C( 43223), UINT16_C( 23928), UINT16_C( 20321), UINT16_C( 51743), UINT16_C( 37618), UINT16_C( 65078), UINT16_C( 7253), UINT16_C( 52827), UINT16_C( 55189), @@ -2182,7 +2182,7 @@ test_simde_mm256_avg_epu8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm256_set_epu8(UINT8_C(132), UINT8_C(185), UINT8_C( 15), UINT8_C(235), UINT8_C(102), UINT8_C( 8), UINT8_C(239), UINT8_C(181), UINT8_C( 81), UINT8_C(155), UINT8_C(236), UINT8_C(191), @@ -2391,7 +2391,7 @@ test_simde_mm256_avg_epu16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm256_set_epu16(UINT16_C( 33977), UINT16_C( 4075), UINT16_C( 26120), UINT16_C( 61365), UINT16_C( 20891), UINT16_C( 60607), UINT16_C( 34113), UINT16_C( 18728), UINT16_C( 46422), UINT16_C( 18901), UINT16_C( 21788), UINT16_C( 13793), @@ -2504,7 +2504,7 @@ test_simde_mm256_blend_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi16(INT16_C( -9012), INT16_C( 17188), INT16_C( 20170), INT16_C( -6948), INT16_C( 9138), INT16_C( 24690), INT16_C( -6761), INT16_C( -2618), INT16_C( 30583), INT16_C( 3343), INT16_C( -2458), INT16_C( 32235), @@ -2617,7 +2617,7 @@ test_simde_mm256_blend_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( 67571941), INT32_C(-1405773426), INT32_C( 1540271825), INT32_C( 2065572299), INT32_C( -582398487), INT32_C( 1269568238), INT32_C( -277360429), INT32_C( 355946014)), simde_mm256_set_epi32(INT32_C(-1175528322), INT32_C( -128390122), INT32_C( 1870386786), INT32_C( 1369967555), @@ -2683,7 +2683,7 @@ test_simde_mm256_blendv_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i b; simde__m256i i; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C( 119), INT8_C( 14), INT8_C( 127), INT8_C(-117), INT8_C( -92), INT8_C( 49), INT8_C( -15), INT8_C( -64), INT8_C( 66), INT8_C(-125), INT8_C( 43), INT8_C( 6), @@ -2956,7 +2956,7 @@ test_simde_mm256_cmpeq_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8( INT8_C( -34), INT8_C( 65), INT8_C( -18), INT8_C( -94), INT8_C( 20), INT8_C(-105), INT8_C( 79), INT8_C( -26), INT8_C( 7), INT8_C( -36), INT8_C( 33), INT8_C( 123), @@ -3165,7 +3165,7 @@ test_simde_mm256_cmpeq_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi16( INT16_C( -5413), INT16_C( -8669), INT16_C(-20019), INT16_C( 13281), INT16_C( 31513), INT16_C( 29495), INT16_C( 24515), INT16_C( -4843), INT16_C(-25942), INT16_C(-22058), INT16_C( 25862), INT16_C( 17599), @@ -3278,7 +3278,7 @@ test_simde_mm256_cmpeq_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32( INT32_C( -566104414), INT32_C( 345460710), INT32_C( 131867003), INT32_C( 1942789694), INT32_C( 1084566886), INT32_C( 361879538), INT32_C( 1536563030), INT32_C(-1809647830)), simde_mm256_set_epi32( INT32_C( 1749780765), INT32_C( -245413822), INT32_C( 131867003), INT32_C( -777848334), @@ -3343,7 +3343,7 @@ test_simde_mm256_cmpeq_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x( INT64_C( 5666986029204224795), INT64_C( 4139191150084672711), INT64_C(-2995542033801296871), INT64_C( 2916699395471658679)), simde_mm256_set_epi64x( INT64_C( 5666986029204224795), INT64_C(-4286656252876457389), @@ -3408,7 +3408,7 @@ test_simde_mm256_cmpgt_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C( 97), INT8_C( 38), INT8_C( 50), INT8_C( -69), INT8_C(-120), INT8_C( 113), INT8_C( -33), INT8_C( -11), INT8_C( 68), INT8_C( 95), INT8_C( 30), INT8_C( 12), @@ -3617,7 +3617,7 @@ test_simde_mm256_cmpgt_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi16(INT16_C( 22495), INT16_C( -4666), INT16_C( 11364), INT16_C( 3408), INT16_C( -7753), INT16_C( 22355), INT16_C( 25225), INT16_C(-16816), INT16_C( 30843), INT16_C( 15445), INT16_C(-14188), INT16_C( 18672), @@ -3730,7 +3730,7 @@ test_simde_mm256_cmpgt_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C(-1910963751), INT32_C(-1037527336), INT32_C( -581253082), INT32_C( -805157505), INT32_C( 1446966287), INT32_C( -8913681), INT32_C( -494526366), INT32_C(-1857474161)), simde_mm256_set_epi32(INT32_C(-1143050049), INT32_C(-1545949366), INT32_C( 1503277288), INT32_C(-1357138171), @@ -3795,7 +3795,7 @@ test_simde_mm256_cmpgt_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C( 2118945800826688975), INT64_C(-2048024407550915063), INT64_C( 5214505670652994271), INT64_C( -257856994503089701)), simde_mm256_set_epi64x(INT64_C( 5695011750507465952), INT64_C( -909596801509157384), @@ -3939,7 +3939,7 @@ test_simde_mm256_broadcastb_epi8(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi8(INT8_C( -20), INT8_C( 103), INT8_C( -20), INT8_C( 116), INT8_C( -9), INT8_C( 73), INT8_C( 44), INT8_C( 79), INT8_C( -20), INT8_C( -81), INT8_C(-114), INT8_C( -81), @@ -4099,7 +4099,7 @@ test_simde_mm256_broadcastw_epi16(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi16(INT16_C(-14724), INT16_C(-11263), INT16_C(-14102), INT16_C( 6431), INT16_C( 11838), INT16_C( -2695), INT16_C(-11290), INT16_C( 22147)), simde_mm256_set_epi16(INT16_C( 22147), INT16_C( 22147), INT16_C( 22147), INT16_C( 22147), @@ -4195,7 +4195,7 @@ test_simde_mm256_broadcastd_epi32(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi32(INT32_C( -964897791), INT32_C( -924182241), INT32_C( 775878009), INT32_C( -739879293)), simde_mm256_set_epi32(INT32_C( -739879293), INT32_C( -739879293), INT32_C( -739879293), INT32_C( -739879293), INT32_C( -739879293), INT32_C( -739879293), INT32_C( -739879293), INT32_C( -739879293)) }, @@ -4267,7 +4267,7 @@ test_simde_mm256_broadcastq_epi64(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi64x(INT64_C(-4144204452956858081), INT64_C( 3332370677895681667)), simde_mm256_set_epi64x(INT64_C( 3332370677895681667), INT64_C( 3332370677895681667), INT64_C( 3332370677895681667), INT64_C( 3332370677895681667)) }, @@ -4339,7 +4339,7 @@ test_simde_mm256_broadcastss_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_ps(SIMDE_FLOAT32_C( 550.68), SIMDE_FLOAT32_C( 569.64), SIMDE_FLOAT32_C( -638.70), SIMDE_FLOAT32_C( 655.47)), simde_mm256_set_ps(SIMDE_FLOAT32_C( 655.47), SIMDE_FLOAT32_C( 655.47), SIMDE_FLOAT32_C( 655.47), SIMDE_FLOAT32_C( 655.47), @@ -4431,7 +4431,7 @@ test_simde_mm256_broadcastsd_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_pd(SIMDE_FLOAT64_C( -638.70), SIMDE_FLOAT64_C( 655.47)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 655.47), SIMDE_FLOAT64_C( 655.47), SIMDE_FLOAT64_C( 655.47), SIMDE_FLOAT64_C( 655.47)) }, @@ -4471,7 +4471,7 @@ test_simde_mm256_broadcastsi128_si256(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi64x (INT64_C( 3783485884510153131), INT64_C( 5322848723863790661)), simde_mm256_set_epi64x(INT64_C( 3783485884510153131), INT64_C( 5322848723863790661), INT64_C( 3783485884510153131), INT64_C( 5322848723863790661)) }, @@ -4645,7 +4645,7 @@ test_simde_mm256_cvtepi8_epi16(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi8(INT8_C( -64), INT8_C( -39), INT8_C( -1), INT8_C( 123), INT8_C( -41), INT8_C( 42), INT8_C( -42), INT8_C( 48), INT8_C(-101), INT8_C( -11), INT8_C( 78), INT8_C( -33), @@ -4725,7 +4725,7 @@ test_simde_mm256_cvtepi8_epi32(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi8(INT8_C( 123), INT8_C( -2), INT8_C( 102), INT8_C( -48), INT8_C( 12), INT8_C(-119), INT8_C( -32), INT8_C( 68), INT8_C( -88), INT8_C( 80), INT8_C( 32), INT8_C(-108), @@ -4789,7 +4789,7 @@ test_simde_mm256_cvtepi8_epi64(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi8(INT8_C( 9), INT8_C( -74), INT8_C( -52), INT8_C( -68), INT8_C( 95), INT8_C( -10), INT8_C( -99), INT8_C( 121), INT8_C( 1), INT8_C( 69), INT8_C( -36), INT8_C(-102), @@ -4854,7 +4854,7 @@ test_simde_mm256_cvtepi16_epi32(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi16(INT16_C( 29201), INT16_C( 17763), INT16_C( 13480), INT16_C( 29487), INT16_C( -6581), INT16_C( 13446), INT16_C( 26538), INT16_C( -3936)), simde_mm256_set_epi32(INT32_C( 29201), INT32_C( 17763), INT32_C( 13480), INT32_C( 29487), @@ -4902,7 +4902,7 @@ test_simde_mm256_cvtepi16_epi64(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi16(INT16_C(-31485), INT16_C( 6767), INT16_C( -1054), INT16_C(-15390), INT16_C(-10897), INT16_C(-31336), INT16_C( -9551), INT16_C( 8617)), simde_mm256_set_epi64x(INT64_C( -10897), INT64_C( -31336), @@ -4950,7 +4950,7 @@ test_simde_mm256_cvtepi32_epi64(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi32(INT32_C( 2035310840), INT32_C( 817509407), INT32_C( 1530478738), INT32_C( 1934275633)), simde_mm256_set_epi64x(INT64_C( 2035310840), INT64_C( 817509407), INT64_C( 1530478738), INT64_C( 1934275633)) }, @@ -4990,7 +4990,7 @@ test_simde_mm256_cvtepu8_epi16(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm_set_epu8(UINT8_C(240), UINT8_C( 50), UINT8_C(144), UINT8_C( 4), UINT8_C( 7), UINT8_C(233), UINT8_C(157), UINT8_C( 74), UINT8_C(217), UINT8_C( 90), UINT8_C(141), UINT8_C(254), @@ -5070,7 +5070,7 @@ test_simde_mm256_cvtepu8_epi32(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm_set_epu8(UINT8_C(240), UINT8_C( 50), UINT8_C(144), UINT8_C( 4), UINT8_C( 7), UINT8_C(233), UINT8_C(157), UINT8_C( 74), UINT8_C(217), UINT8_C( 90), UINT8_C(141), UINT8_C(254), @@ -5134,7 +5134,7 @@ test_simde_mm256_cvtepu8_epi64(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm_set_epu8(UINT8_C( 9), UINT8_C(182), UINT8_C(204), UINT8_C(188), UINT8_C( 95), UINT8_C(246), UINT8_C(157), UINT8_C(121), UINT8_C( 1), UINT8_C( 69), UINT8_C(220), UINT8_C(154), @@ -5198,7 +5198,7 @@ test_simde_mm256_cvtepu16_epi32(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm_set_epu16(UINT16_C(61490), UINT16_C(36868), UINT16_C( 2025), UINT16_C(40266), UINT16_C(55642), UINT16_C(36350), UINT16_C(29536), UINT16_C(32279)), simde_mm256_set_epi32(INT32_C( 61490), INT32_C( 36868), INT32_C( 2025), INT32_C( 40266), @@ -5246,7 +5246,7 @@ test_simde_mm256_cvtepu16_epi64(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm_set_epu16(UINT16_C(61490), UINT16_C(36868), UINT16_C( 2025), UINT16_C(40266), UINT16_C(55642), UINT16_C(36350), UINT16_C(29536), UINT16_C(32279)), simde_mm256_set_epi64x(INT64_C( 55642), INT64_C( 36350), @@ -5294,7 +5294,7 @@ test_simde_mm256_cvtepu32_epi64(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm_set_epu32(UINT32_C(2027668512), UINT32_C(4262540660), UINT32_C(2279720356), UINT32_C( 579063940)), simde_mm256_set_epi64x(INT64_C( 2027668512), INT64_C( 4262540660), INT64_C( 2279720356), INT64_C( 579063940)) }, @@ -5478,7 +5478,7 @@ test_simde_mm256_extracti128_si256(SIMDE_MUNIT_TEST_ARGS) { simde__m256i b; simde__m128i ra; simde__m128i rb; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( 1229394801), INT32_C( 992221618), INT32_C(-1388107406), INT32_C( 780445625), INT32_C( 1795700153), INT32_C( -297324271), INT32_C( 1549329146), INT32_C( -534963225)), simde_mm256_set_epi32(INT32_C( -867719772), INT32_C(-1804212438), INT32_C( 1849818353), INT32_C( 405560893), @@ -5545,7 +5545,7 @@ test_simde_mm256_hadd_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi16(INT16_C(-18444), INT16_C(-18028), INT16_C( 29026), INT16_C( 2084), INT16_C( 4112), INT16_C(-30013), INT16_C( 26536), INT16_C(-22613), INT16_C( 28256), INT16_C(-13992), INT16_C( 1054), INT16_C(-17387), @@ -5658,7 +5658,7 @@ test_simde_mm256_hadd_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C(-1208698476), INT32_C( 1902250020), INT32_C( 269519555), INT32_C( 1739106219), INT32_C( 1851836760), INT32_C( 69123093), INT32_C( 1858718140), INT32_C(-1547967184)), simde_mm256_set_epi32(INT32_C( -136086179), INT32_C(-2103379839), INT32_C(-1938290984), INT32_C( -619951923), @@ -5790,7 +5790,7 @@ test_simde_mm256_hsub_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi16(INT16_C(-18444), INT16_C(-18028), INT16_C( 29026), INT16_C( 2084), INT16_C( 4112), INT16_C(-30013), INT16_C( 26536), INT16_C(-22613), INT16_C( 28256), INT16_C(-13992), INT16_C( 1054), INT16_C(-17387), @@ -5903,7 +5903,7 @@ test_simde_mm256_hsub_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C(-1208698476), INT32_C( 1902250020), INT32_C( 269519555), INT32_C( 1739106219), INT32_C( 1851836760), INT32_C( 69123093), INT32_C( 1858718140), INT32_C(-1547967184)), simde_mm256_set_epi32(INT32_C( -136086179), INT32_C(-2103379839), INT32_C(-1938290984), INT32_C( -619951923), @@ -7542,7 +7542,7 @@ test_simde_mm256_madd_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi16(INT16_C(-22074), INT16_C( 27892), INT16_C(-27402), INT16_C( -5185), INT16_C(-13617), INT16_C( 6733), INT16_C( 31914), INT16_C( 16627), INT16_C( 14296), INT16_C( 527), INT16_C(-18797), INT16_C( 25549), @@ -8140,7 +8140,7 @@ test_simde_mm256_max_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C( 82), INT8_C( 80), INT8_C( 100), INT8_C(-114), INT8_C(-121), INT8_C(-115), INT8_C( -33), INT8_C( -36), INT8_C(-105), INT8_C( -52), INT8_C( 94), INT8_C( 97), @@ -8350,7 +8350,7 @@ test_simde_mm256_max_epu8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm256_set_epu8(UINT8_C(180), UINT8_C(215), UINT8_C( 58), UINT8_C(173), UINT8_C(238), UINT8_C(242), UINT8_C( 74), UINT8_C(116), UINT8_C(237), UINT8_C( 59), UINT8_C(170), UINT8_C(217), @@ -8559,7 +8559,7 @@ test_simde_mm256_max_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi16(INT16_C( 13945), INT16_C(-32397), INT16_C( -8500), INT16_C(-16936), INT16_C( -615), INT16_C( 28879), INT16_C( 19952), INT16_C(-20844), INT16_C(-18762), INT16_C( 23311), INT16_C(-22090), INT16_C( 16355), @@ -8672,7 +8672,7 @@ test_simde_mm256_max_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C(-1578701412), INT32_C(-1861943275), INT32_C( 1717826073), INT32_C( -689858277), INT32_C(-2120069619), INT32_C( -269745295), INT32_C( 993893699), INT32_C( 1747535129)), simde_mm256_set_epi32(INT32_C(-1662415513), INT32_C( 528745592), INT32_C( -219858588), INT32_C( 622357704), @@ -8737,7 +8737,7 @@ test_simde_mm256_min_epu8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm256_set_epu8(UINT8_C( 83), UINT8_C( 77), UINT8_C(142), UINT8_C(252), UINT8_C( 19), UINT8_C( 26), UINT8_C(193), UINT8_C( 92), UINT8_C(253), UINT8_C(183), UINT8_C(225), UINT8_C(205), @@ -8946,7 +8946,7 @@ test_simde_mm256_min_epu16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm256_set_epu16(UINT16_C( 21985), UINT16_C( 37408), UINT16_C( 64559), UINT16_C( 50506), UINT16_C( 21348), UINT16_C( 50917), UINT16_C( 43331), UINT16_C( 4092), UINT16_C( 58372), UINT16_C( 9106), UINT16_C( 30380), UINT16_C( 36427), @@ -9059,7 +9059,7 @@ test_simde_mm256_min_epu32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm256_set_epu32(UINT32_C(1967336836), UINT32_C(4229175532), UINT32_C(3383228965), UINT32_C( 979444700), UINT32_C( 138906106), UINT32_C( 146006389), UINT32_C(2494756173), UINT32_C(2105904126)), simde_x_mm256_set_epu32(UINT32_C(2893387611), UINT32_C(2460478173), UINT32_C(3299027518), UINT32_C( 896184310), @@ -9123,7 +9123,7 @@ test_simde_mm256_movemask_epi8(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; int32_t r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C( -96), INT8_C(-118), INT8_C( 98), INT8_C( 62), INT8_C( -51), INT8_C( 97), INT8_C( -33), INT8_C( 125), INT8_C(-127), INT8_C( -72), INT8_C( -2), INT8_C( 75), @@ -9598,7 +9598,7 @@ test_simde_mm256_mullo_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi16(INT16_C( 26958), INT16_C( 5839), INT16_C( 10773), INT16_C(-17217), INT16_C( 20782), INT16_C(-24278), INT16_C( 14053), INT16_C( 4872), INT16_C(-31512), INT16_C( -5844), INT16_C( 1857), INT16_C( 9311), @@ -9711,7 +9711,7 @@ test_simde_mm256_mullo_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C(-1352403780), INT32_C( -343467662), INT32_C( 517643457), INT32_C( -488960691), INT32_C(-1266352672), INT32_C( 1517008609), INT32_C( 990411931), INT32_C(-1870795966)), simde_mm256_set_epi32(INT32_C(-1381411484), INT32_C(-1688230631), INT32_C( 2122460393), INT32_C( 1331099088), @@ -9776,7 +9776,7 @@ test_simde_x_mm256_mullo_epu32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm256_set_epu32(UINT32_C(2258322750), UINT32_C(2861166599), UINT32_C(3174424968), UINT32_C(2016553993), UINT32_C(2997181236), UINT32_C( 363976099), UINT32_C(1103728177), UINT32_C(2198010875)), simde_x_mm256_set_epu32(UINT32_C(1159500967), UINT32_C(2653222606), UINT32_C(3215542902), UINT32_C(2811870533), @@ -9841,7 +9841,7 @@ test_simde_mm256_or_si256(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C( -801044498564576659), INT64_C(-2909946603020252481), INT64_C( 5958340648204315976), INT64_C( 8713768337389103061)), simde_mm256_set_epi64x(INT64_C( 9176724763357309327), INT64_C( 4054644920102546891), @@ -10173,7 +10173,7 @@ test_simde_mm256_permute4x64_epi64(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C(-4031273950158647677), INT64_C(-7434948453373431243), INT64_C( 966046851086666502), INT64_C(-3558090175042735721)), simde_mm256_set_epi64x(INT64_C(-3558090175042735721), INT64_C(-3558090175042735721), @@ -10221,7 +10221,7 @@ test_simde_mm256_permute4x64_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -641.76), SIMDE_FLOAT64_C( 477.18), SIMDE_FLOAT64_C( 278.49), SIMDE_FLOAT64_C( 569.18)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 569.18), SIMDE_FLOAT64_C( 569.18), @@ -10270,7 +10270,7 @@ test_simde_mm256_permute2x128_si256(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C( 9096692030846176105), INT64_C( 644260392039444522), INT64_C(-4583540275174352405), INT64_C(-6816753880857675259)), simde_mm256_set_epi64x(INT64_C(-7886827988827131690), INT64_C(-2107575233125845054), @@ -10549,7 +10549,7 @@ test_simde_mm256_shuffle_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm256_set_epu8(UINT8_C(132), UINT8_C(100), UINT8_C(115), UINT8_C( 94), UINT8_C( 73), UINT8_C(247), UINT8_C(104), UINT8_C(220), UINT8_C(117), UINT8_C( 74), UINT8_C( 39), UINT8_C(125), @@ -10757,7 +10757,7 @@ test_simde_mm256_shuffle_epi32(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( 7953530), INT32_C( 1626445648), INT32_C( 338474584), INT32_C( 1314132322), INT32_C( -165526664), INT32_C( 1862544223), INT32_C( 1736492928), INT32_C( -812721862)), simde_mm256_set_epi32(INT32_C( 1626445648), INT32_C( 1626445648), INT32_C( 1626445648), INT32_C( 1626445648), @@ -10854,7 +10854,7 @@ test_simde_mm256_shufflelo_epi16(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi16(INT16_C( -2179), INT16_C( 30608), INT16_C( 19808), INT16_C(-28307), INT16_C( 25873), INT16_C( -9642), INT16_C( 56), INT16_C( 338), INT16_C(-29256), INT16_C( 9693), INT16_C( 18909), INT16_C( 3915), @@ -10935,7 +10935,7 @@ test_simde_mm256_sign_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C(-124), INT8_C( -48), INT8_C( 10), INT8_C( 63), INT8_C( -84), INT8_C( 103), INT8_C( -14), INT8_C( 63), INT8_C( 82), INT8_C( -68), INT8_C( -17), INT8_C( 117), @@ -11144,7 +11144,7 @@ test_simde_mm256_sign_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi16(INT16_C(-31536), INT16_C( 2623), INT16_C(-21401), INT16_C( -3521), INT16_C( 21180), INT16_C( -4235), INT16_C(-20328), INT16_C( 9531), INT16_C( 30987), INT16_C( -4902), INT16_C( 9409), INT16_C(-22567), @@ -11257,7 +11257,7 @@ test_simde_mm256_sign_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C(-2066740673), INT32_C(-1402473921), INT32_C( 1388113781), INT32_C(-1332206277), INT32_C( 2030824666), INT32_C( 616671193), INT32_C( 1932233736), INT32_C(-1125047369)), simde_mm256_set_epi32(INT32_C( 1087531093), INT32_C(-1100485211), INT32_C(-1940507046), INT32_C(-2139586601), @@ -11466,7 +11466,7 @@ test_simde_mm256_slli_epi16(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m256i r; - } test_vec[] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[] = { { simde_mm256_set_epi16(INT16_C( -7189), INT16_C( -4038), INT16_C( 8832), INT16_C(-31599), INT16_C( 9071), INT16_C(-26166), INT16_C( 4984), INT16_C(-29916), INT16_C( 26692), INT16_C( 7557), INT16_C(-30970), INT16_C(-31903), @@ -11656,7 +11656,7 @@ test_simde_mm256_slli_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( 1857969468), INT32_C( 1569141389), INT32_C(-1894985594), INT32_C( 1398609693), INT32_C( 1177229575), INT32_C( 1655079421), INT32_C(-1753400065), INT32_C( -607538910)), simde_mm256_set_epi32(INT32_C(-1434991502), INT32_C(-1643531728), INT32_C( 1435031148), INT32_C( -241637048), @@ -11721,7 +11721,7 @@ test_simde_mm256_slli_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C(-1180812000753094585), INT64_C(-5675573813228216402), INT64_C(-2208027268370360000), INT64_C( 6465428915389083026)), simde_mm256_set_epi64x(INT64_C( 8452611756027991400), INT64_C(-5020149848375082542), @@ -11908,7 +11908,7 @@ test_simde_mm256_sllv_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( -907599535), INT32_C( 1816850761), INT32_C(-1813723808), INT32_C( 1682346964), INT32_C( 297464492), INT32_C( 1204833268), INT32_C(-2121860190), INT32_C( 1275339488)), simde_mm256_set_epi32(INT32_C( 26), INT32_C( 9), INT32_C( 13), INT32_C( 1136705026), @@ -12014,7 +12014,7 @@ test_simde_mm256_sllv_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C( -91881763986021568), INT64_C( 8531978069693998286), INT64_C( 7972759472039988968), INT64_C(-4018394183250543798)), simde_mm256_set_epi64x(INT64_C( 3), INT64_C( 44), @@ -12187,7 +12187,7 @@ test_simde_mm256_srai_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i r15; simde__m256i r16; simde__m256i r24; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi16(INT16_C( 15196), INT16_C(-26519), INT16_C( 2034), INT16_C( 3767), INT16_C( 20039), INT16_C( 24955), INT16_C( -829), INT16_C( 24412), INT16_C( 5644), INT16_C(-14035), INT16_C( 32481), INT16_C(-26971), @@ -12515,7 +12515,7 @@ test_simde_mm256_srai_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i r31; simde__m256i r32; simde__m256i r55; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( 995924073), INT32_C( 133303991), INT32_C( 1313300859), INT32_C( -54304932), INT32_C( 369936685), INT32_C( 2128713381), INT32_C( -853171060), INT32_C( -927487564)), simde_mm256_set_epi32(INT32_C( 497962036), INT32_C( 66651995), INT32_C( 656650429), INT32_C( -27152466), @@ -12930,7 +12930,7 @@ test_simde_mm256_srli_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i r15; simde__m256i r16; simde__m256i r24; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi16(INT16_C(-13208), INT16_C( 32518), INT16_C(-12083), INT16_C( -4650), INT16_C( 32616), INT16_C(-23415), INT16_C(-12219), INT16_C(-11043), INT16_C( 17138), INT16_C( 18141), INT16_C( 29257), INT16_C(-17957), @@ -13252,7 +13252,7 @@ test_simde_mm256_srli_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( 732419944), INT32_C( -77147012), INT32_C( 489295522), INT32_C( -707244875), INT32_C( 1759674836), INT32_C( 934163130), INT32_C( 1804082267), INT32_C(-1601331496)), simde_mm256_set_epi32(INT32_C( 849157488), INT32_C( 1818223314), INT32_C( -155475303), INT32_C(-1398665928), @@ -13316,7 +13316,7 @@ test_simde_mm256_srli_epi64(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(HEDLEY_STATIC_CAST(int64_t, UINT64_C(13444540030250453406)), HEDLEY_STATIC_CAST(int64_t, UINT64_C( 3078071440592676417)), HEDLEY_STATIC_CAST(int64_t, UINT64_C(12679412335333608791)), HEDLEY_STATIC_CAST(int64_t, UINT64_C(11535715936901372554))), simde_mm256_set_epi64x(HEDLEY_STATIC_CAST(int64_t, UINT64_C( 1641179202911432)), HEDLEY_STATIC_CAST(int64_t, UINT64_C( 375741142650473)), @@ -13364,7 +13364,7 @@ test_simde_mm256_srli_si256(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C( 96), INT8_C( 17), INT8_C( 11), INT8_C( 103), INT8_C( 75), INT8_C( 47), INT8_C( -18), INT8_C( 1), INT8_C( 93), INT8_C( -43), INT8_C( -55), INT8_C( 100), @@ -13550,7 +13550,7 @@ test_simde_mm256_srlv_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( 861771480), INT32_C( 1241239464), INT32_C( 563960678), INT32_C(-1557457802), INT32_C( 750889845), INT32_C( 1061237522), INT32_C( -532194576), INT32_C( 369438034)), simde_mm256_set_epi32(INT32_C( 31), INT32_C( 28), INT32_C( 8), INT32_C(-1408300382), @@ -13656,7 +13656,7 @@ test_simde_mm256_srlv_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C( 3701280324466757544), INT64_C( 2422192670977496182), INT64_C( 3225047328234746642), INT64_C(-2285758298659148462)), simde_mm256_set_epi64x(INT64_C( 28), INT64_C( 34), @@ -13723,7 +13723,7 @@ test_simde_mm256_stream_load_si256 (SIMDE_MUNIT_TEST_ARGS) { const struct { SIMDE_ALIGN_LIKE_32(simde__m256i) const int32_t a[8]; const int32_t r[8]; - } test_vec[] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[] = { { { -INT32_C( 318278464), -INT32_C( 1120465675), INT32_C( 457266700), INT32_C( 2139701695), INT32_C( 1033159662), -INT32_C( 359675734), INT32_C( 1714257348), INT32_C( 1256709514) }, { -INT32_C( 318278464), -INT32_C( 1120465675), INT32_C( 457266700), INT32_C( 2139701695), INT32_C( 1033159662), -INT32_C( 359675734), INT32_C( 1714257348), INT32_C( 1256709514) } }, { { INT32_C( 1178070609), INT32_C( 117731066), -INT32_C( 2094905916), INT32_C( 1963174791), INT32_C( 431200111), INT32_C( 587416159), INT32_C( 1233793215), INT32_C( 1586786573) }, @@ -13756,7 +13756,7 @@ test_simde_mm256_sub_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C( -37), INT8_C( -5), INT8_C( -23), INT8_C( 84), INT8_C(-108), INT8_C( -92), INT8_C( 86), INT8_C( -77), INT8_C( 77), INT8_C( -93), INT8_C( -37), INT8_C( 101), @@ -13965,7 +13965,7 @@ test_simde_mm256_sub_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi16(INT16_C(-27953), INT16_C(-25893), INT16_C( 18102), INT16_C( -6593), INT16_C( 7623), INT16_C( 27326), INT16_C(-15847), INT16_C( 25196), INT16_C( 4150), INT16_C( 31494), INT16_C( 14922), INT16_C( 2426), @@ -14078,7 +14078,7 @@ test_simde_mm256_sub_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( 326943318), INT32_C(-1426446841), INT32_C( -705322739), INT32_C( 1382181134), INT32_C( -752013979), INT32_C( 1926838871), INT32_C(-1267474220), INT32_C(-1807600682)), simde_mm256_set_epi32(INT32_C( 251701658), INT32_C( 1304570849), INT32_C(-1313346575), INT32_C( 548342496), @@ -14143,7 +14143,7 @@ test_simde_mm256_sub_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C(-2885858146882597019), INT64_C(-3498254024691385676), INT64_C( 7972223233728178657), INT64_C( 6231317733982512179)), simde_mm256_set_epi64x(INT64_C( 3826502112888397679), INT64_C(-8682306207824752089), @@ -14208,7 +14208,7 @@ test_simde_x_mm256_sub_epu32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm256_set_epu32(UINT32_C( 107879378), UINT32_C(2256216441), UINT32_C(1547145394), UINT32_C( 23322183), UINT32_C( 24183335), UINT32_C(2032217709), UINT32_C( 971024796), UINT32_C(3326705122)), simde_x_mm256_set_epu32(UINT32_C( 149466069), UINT32_C(3517994125), UINT32_C(1432270320), UINT32_C(2851287457), @@ -14273,7 +14273,7 @@ test_simde_mm256_subs_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C( 53), INT8_C( 22), INT8_C( -99), INT8_C( -90), INT8_C( 42), INT8_C( 84), INT8_C( 24), INT8_C( 60), INT8_C(-122), INT8_C( 44), INT8_C( -82), INT8_C( 91), @@ -14482,7 +14482,7 @@ test_simde_mm256_subs_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi16(INT16_C( 13590), INT16_C(-25178), INT16_C( 10836), INT16_C( 6204), INT16_C(-31188), INT16_C(-20901), INT16_C(-14955), INT16_C(-18273), INT16_C(-29119), INT16_C(-17708), INT16_C( -8621), INT16_C( 7683), @@ -14595,7 +14595,7 @@ test_simde_mm256_subs_epu8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm256_set_epu8(UINT8_C( 53), UINT8_C( 22), UINT8_C(157), UINT8_C(166), UINT8_C( 42), UINT8_C( 84), UINT8_C( 24), UINT8_C( 60), UINT8_C(134), UINT8_C( 44), UINT8_C(174), UINT8_C( 91), @@ -14804,7 +14804,7 @@ test_simde_mm256_subs_epu16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm256_set_epu16(UINT16_C( 13590), UINT16_C( 40358), UINT16_C( 10836), UINT16_C( 6204), UINT16_C( 34348), UINT16_C( 44635), UINT16_C( 50581), UINT16_C( 47263), UINT16_C( 36417), UINT16_C( 47828), UINT16_C( 56915), UINT16_C( 7683), @@ -14917,7 +14917,7 @@ test_simde_mm256_unpacklo_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C(-101), INT8_C( 92), INT8_C( -29), INT8_C( 114), INT8_C( -9), INT8_C( 115), INT8_C( -85), INT8_C( 76), INT8_C( 113), INT8_C( 104), INT8_C( 13), INT8_C( 120), @@ -15126,7 +15126,7 @@ test_simde_mm256_unpacklo_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi16(INT16_C(-30282), INT16_C( 17545), INT16_C( 1397), INT16_C(-23688), INT16_C( 7095), INT16_C(-13226), INT16_C( 16225), INT16_C( 24624), INT16_C(-19105), INT16_C( 16354), INT16_C(-30269), INT16_C(-10683), @@ -15239,7 +15239,7 @@ test_simde_mm256_unpacklo_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( 1634006754), INT32_C( 2027673276), INT32_C(-1004966058), INT32_C( 31035471), INT32_C( 582697150), INT32_C( -865564811), INT32_C(-1835008447), INT32_C( 1804896535)), simde_mm256_set_epi32(INT32_C( 250556499), INT32_C(-1998071312), INT32_C(-1032788603), INT32_C(-1564323608), @@ -15304,7 +15304,7 @@ test_simde_mm256_unpacklo_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C( 7018005571900790460), INT64_C(-4316296352669003697), INT64_C( 2502665206151808885), INT64_C(-7881301265943852777)), simde_mm256_set_epi64x(INT64_C( 1076131971302152688), INT64_C(-4435793270835883800), @@ -15369,7 +15369,7 @@ test_simde_mm256_unpackhi_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C( 87), INT8_C( 102), INT8_C( -8), INT8_C( -64), INT8_C( 127), INT8_C( 58), INT8_C( 96), INT8_C( 103), INT8_C( -98), INT8_C(-118), INT8_C( 55), INT8_C( 100), @@ -15578,7 +15578,7 @@ test_simde_mm256_unpackhi_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi16(INT16_C( 28196), INT16_C(-19354), INT16_C( 9804), INT16_C(-14507), INT16_C(-13536), INT16_C( 20917), INT16_C( 967), INT16_C(-20246), INT16_C(-10186), INT16_C( -9535), INT16_C(-21783), INT16_C( 1947), @@ -15691,7 +15691,7 @@ test_simde_mm256_unpackhi_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( 1912850859), INT32_C( 967654585), INT32_C( 1199101495), INT32_C( 1020867807), INT32_C(-1113017403), INT32_C( 1207205853), INT32_C(-1283015323), INT32_C( -865603422)), simde_mm256_set_epi32(INT32_C( 439671122), INT32_C( -834176430), INT32_C( 1316719462), INT32_C( 794894521), @@ -15756,7 +15756,7 @@ test_simde_mm256_unpackhi_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C( 8215631882498161849), INT64_C( 5150101706630575327), INT64_C(-4780373344556646435), INT64_C(-5510508849122512734)), simde_mm256_set_epi64x(INT64_C( 1888373093446416978), INT64_C( 5655267028091609273), @@ -15821,7 +15821,7 @@ test_simde_mm256_xor_si256(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C( 5259297934522696228), INT64_C( -431388325374833226), INT64_C(-9156654280217339654), INT64_C( 3013799969040676174)), simde_mm256_set_epi64x(INT64_C(-5610681863545377343), INT64_C( 612481038911101319), @@ -15886,7 +15886,7 @@ test_simde_mm256_max_epu16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm256_set_epu16(UINT16_C( 46627), UINT16_C( 59720), UINT16_C( 61906), UINT16_C( 11658), UINT16_C( 20044), UINT16_C( 39774), UINT16_C( 13081), UINT16_C( 26580), UINT16_C( 18209), UINT16_C( 20949), UINT16_C( 29177), UINT16_C( 31372), @@ -16000,7 +16000,7 @@ test_simde_mm256_max_epu32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm256_set_epu32(UINT32_C(3051572045), UINT32_C(3545123096), UINT32_C( 539532434), UINT32_C(2726067579), UINT32_C(3419329411), UINT32_C(3056421163), UINT32_C(2937475413), UINT32_C( 891304178)), simde_x_mm256_set_epu32(UINT32_C(3684521838), UINT32_C(3664092042), UINT32_C( 648541541), UINT32_C( 272930365), @@ -16106,7 +16106,7 @@ test_simde_mm256_min_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C(-113), INT8_C( 124), INT8_C( 15), INT8_C(-126), INT8_C( -14), INT8_C( -39), INT8_C( -2), INT8_C( -33), INT8_C( 77), INT8_C(-107), INT8_C( -95), INT8_C( -10), @@ -16315,7 +16315,7 @@ test_simde_mm256_min_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi16(INT16_C(-28804), INT16_C( 3970), INT16_C( -3367), INT16_C( -289), INT16_C( 19861), INT16_C(-24074), INT16_C( 6311), INT16_C( 20549), INT16_C(-25290), INT16_C( 1383), INT16_C( 18187), INT16_C(-10374), @@ -16428,7 +16428,7 @@ test_simde_mm256_min_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C(-1887694974), INT32_C( -220594465), INT32_C( 1301651958), INT32_C( 413618245), INT32_C(-1657404057), INT32_C( 1191958394), INT32_C( 967153179), INT32_C( 972617254)), simde_mm256_set_epi32(INT32_C( 982854550), INT32_C(-2124977293), INT32_C( 1533583803), INT32_C( -612489163), diff --git a/test/x86/avx512/abs.c b/test/x86/avx512/abs.c index 0fbde45ef..24af5040e 100644 --- a/test/x86/avx512/abs.c +++ b/test/x86/avx512/abs.c @@ -485,7 +485,7 @@ test_simde_mm256_abs_epi64(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C( 2298255581870375211), INT64_C(-3544843370875867424), INT64_C( 3174188203889017774), INT64_C(-2855144460944446932)), simde_mm256_set_epi64x(INT64_C( 2298255581870375211), INT64_C( 3544843370875867424), @@ -535,7 +535,7 @@ test_simde_mm256_mask_abs_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C( 623879162816280883), INT64_C(-3225900025883395735), INT64_C( 411040496809638529), INT64_C(-7584870799288762128)), UINT8_C( 62), @@ -608,7 +608,7 @@ test_simde_mm256_maskz_abs_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 51), simde_mm256_set_epi64x(INT64_C(-5558947899438156608), INT64_C(-5328111225624005045), INT64_C(-5266448436194518899), INT64_C(-3023513724998191945)), @@ -664,7 +664,7 @@ test_simde_mm512_abs_epi8(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( -97), INT8_C( 22), INT8_C( -8), INT8_C(-101), INT8_C( -18), INT8_C( 124), INT8_C( -73), INT8_C( -35), INT8_C(-107), INT8_C( 125), INT8_C( -49), INT8_C( -14), @@ -938,7 +938,7 @@ test_simde_mm512_mask_abs_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__mmask64 k; simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( 117), INT8_C(-104), INT8_C( -35), INT8_C( -40), INT8_C( -1), INT8_C( 43), INT8_C( 10), INT8_C( -45), INT8_C( -42), INT8_C( 80), INT8_C( -69), INT8_C( -15), @@ -1347,7 +1347,7 @@ test_simde_mm512_maskz_abs_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__mmask64 k; simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT64_C( 1713497089), simde_mm512_set_epi8(INT8_C(-105), INT8_C( 80), INT8_C( -16), INT8_C(-124), INT8_C( -48), INT8_C( 76), INT8_C( -91), INT8_C(-128), @@ -1627,7 +1627,7 @@ test_simde_mm512_abs_epi16(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi16(INT16_C(-24810), INT16_C( -1893), INT16_C( -4484), INT16_C(-18467), INT16_C(-27267), INT16_C(-12302), INT16_C(-13826), INT16_C( 938), INT16_C(-17680), INT16_C( -610), INT16_C( -4882), INT16_C(-14649), @@ -1985,7 +1985,7 @@ test_simde_mm512_abs_epi32(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C(-1095158286), INT32_C( -133595553), INT32_C( -941949577), INT32_C(-1117722052), INT32_C(-1053667317), INT32_C( -662420643), INT32_C( 2095193825), INT32_C( -799061081), INT32_C( 347912513), INT32_C( -439299809), INT32_C( 2053030698), INT32_C( -277514113), @@ -2067,7 +2067,7 @@ test_simde_mm512_mask_abs_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( 114710097), INT32_C( 1837246098), INT32_C(-1399577225), INT32_C(-1388127606), INT32_C( 1116027725), INT32_C( -871797325), INT32_C(-1979326643), INT32_C( 1477004857), INT32_C( 1670723749), INT32_C(-1006052339), INT32_C( 1863789116), INT32_C( -690396684), @@ -2188,7 +2188,7 @@ test_simde_mm512_maskz_abs_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(17600), simde_mm512_set_epi32(INT32_C( 393115914), INT32_C( -9604904), INT32_C( 114710097), INT32_C( 1837246098), INT32_C(-1399577225), INT32_C(-1388127606), INT32_C( 1116027725), INT32_C( -871797325), @@ -2276,7 +2276,7 @@ test_simde_mm512_abs_epi64(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C(-4703669018152042913), INT64_C(-4045642624518788548), INT64_C(-4525466663746518179), INT64_C( 8998788960652053415), INT64_C( 1494272869059842335), INT64_C( 8817699709611505791), @@ -2358,7 +2358,7 @@ test_simde_mm512_mask_abs_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C( 492676116973233810), INT64_C(-6011138406694593910), INT64_C( 4793302583727451571), INT64_C(-8501143198309462471), INT64_C( 7175703865894427661), INT64_C( 8004913303465320948), @@ -2479,7 +2479,7 @@ test_simde_mm512_maskz_abs_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C(192), simde_mm512_set_epi64(INT64_C( -41252748446509487), INT64_C( 7890911908509001079), INT64_C(-5961962669328745651), INT64_C(-3744340997299642547), @@ -2567,7 +2567,7 @@ test_simde_mm512_abs_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( 747.74), SIMDE_FLOAT32_C( -874.37), SIMDE_FLOAT32_C( 751.90), SIMDE_FLOAT32_C( -592.77), SIMDE_FLOAT32_C( -708.81), SIMDE_FLOAT32_C( 252.42), SIMDE_FLOAT32_C( -787.46), SIMDE_FLOAT32_C( -882.47), SIMDE_FLOAT32_C( -140.56), SIMDE_FLOAT32_C( -558.99), SIMDE_FLOAT32_C( 240.08), SIMDE_FLOAT32_C( -481.72), @@ -2649,7 +2649,7 @@ test_simde_mm512_mask_abs_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -319.23), SIMDE_FLOAT32_C( 773.21), SIMDE_FLOAT32_C( -25.13), SIMDE_FLOAT32_C( 859.40), SIMDE_FLOAT32_C( -184.67), SIMDE_FLOAT32_C( 833.56), SIMDE_FLOAT32_C( -441.84), SIMDE_FLOAT32_C( -761.98), SIMDE_FLOAT32_C( -874.37), SIMDE_FLOAT32_C( -592.77), SIMDE_FLOAT32_C( 252.42), SIMDE_FLOAT32_C( -882.47), @@ -2769,7 +2769,7 @@ test_simde_mm512_abs_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -140.56), SIMDE_FLOAT64_C( -558.99), SIMDE_FLOAT64_C( 240.08), SIMDE_FLOAT64_C( -481.72), SIMDE_FLOAT64_C( 489.35), SIMDE_FLOAT64_C( 686.76), @@ -2851,7 +2851,7 @@ test_simde_mm512_mask_abs_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -874.37), SIMDE_FLOAT64_C( -592.77), SIMDE_FLOAT64_C( 252.42), SIMDE_FLOAT64_C( -882.47), SIMDE_FLOAT64_C( -558.99), SIMDE_FLOAT64_C( -481.72), diff --git a/test/x86/avx512/adds.c b/test/x86/avx512/adds.c index 7113b324f..9e95c9ee8 100644 --- a/test/x86/avx512/adds.c +++ b/test/x86/avx512/adds.c @@ -773,7 +773,7 @@ test_simde_mm512_adds_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( -30), INT8_C( -16), INT8_C( -64), INT8_C( 113), INT8_C( 51), INT8_C(-115), INT8_C( 19), INT8_C( -80), INT8_C(-110), INT8_C( -62), INT8_C( -91), INT8_C( 8), @@ -1176,7 +1176,7 @@ test_simde_mm512_mask_adds_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( 92), INT8_C( 116), INT8_C( -78), INT8_C( -19), INT8_C( -73), INT8_C( 22), INT8_C( -66), INT8_C( -29), INT8_C( 55), INT8_C( 78), INT8_C( -45), INT8_C(-119), @@ -1714,7 +1714,7 @@ test_simde_mm512_maskz_adds_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT64_C(17286015531074160252), simde_mm512_set_epi8(INT8_C(-115), INT8_C( -27), INT8_C( 62), INT8_C( -85), INT8_C( 49), INT8_C(-115), INT8_C( 38), INT8_C( 4), @@ -2123,7 +2123,7 @@ test_simde_mm512_adds_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi16(INT16_C( 5952), INT16_C(-21138), INT16_C( 23605), INT16_C( -3799), INT16_C( 1987), INT16_C( 29254), INT16_C( -4184), INT16_C( 13346), INT16_C( 26203), INT16_C(-24373), INT16_C( 15487), INT16_C( 15569), @@ -2614,7 +2614,7 @@ test_simde_mm512_adds_epu8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu8(UINT8_C( 52), UINT8_C( 29), UINT8_C( 31), UINT8_C(206), UINT8_C( 40), UINT8_C(160), UINT8_C(244), UINT8_C( 85), UINT8_C( 47), UINT8_C(153), UINT8_C(218), UINT8_C(226), @@ -3017,7 +3017,7 @@ test_simde_mm512_mask_adds_epu8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu8(UINT8_C( 92), UINT8_C( 116), UINT8_C( 178), UINT8_C( 237), UINT8_C( 183), UINT8_C( 22), UINT8_C( 190), UINT8_C( 227), UINT8_C( 55), UINT8_C( 78), UINT8_C( 211), UINT8_C( 137), @@ -3555,7 +3555,7 @@ test_simde_mm512_maskz_adds_epu8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT64_C(17286015531074160252), simde_x_mm512_set_epu8(UINT8_C( 141), UINT8_C( 229), UINT8_C( 62), UINT8_C( 171), UINT8_C( 49), UINT8_C( 141), UINT8_C( 38), UINT8_C( 4), @@ -3964,7 +3964,7 @@ test_simde_mm512_adds_epu16(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu16(UINT16_C( 57245), UINT16_C( 31803), UINT16_C( 9053), UINT16_C( 21282), UINT16_C( 45515), UINT16_C( 57894), UINT16_C( 50445), UINT16_C( 50583), UINT16_C( 54723), UINT16_C( 52144), UINT16_C( 13347), UINT16_C( 57624), diff --git a/test/x86/avx512/and.c b/test/x86/avx512/and.c index 4a7e14f5f..16df19855 100644 --- a/test/x86/avx512/and.c +++ b/test/x86/avx512/and.c @@ -38,7 +38,7 @@ test_simde_mm512_and_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m512 a; simde__m512 b; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( 260.00), SIMDE_FLOAT32_C( 472.07), SIMDE_FLOAT32_C( 343.37), SIMDE_FLOAT32_C( 668.63), SIMDE_FLOAT32_C( 74.64), SIMDE_FLOAT32_C( -166.33), SIMDE_FLOAT32_C( 962.01), SIMDE_FLOAT32_C( 120.25), SIMDE_FLOAT32_C( -633.54), SIMDE_FLOAT32_C( -160.44), SIMDE_FLOAT32_C( -754.35), SIMDE_FLOAT32_C( 920.06), @@ -151,7 +151,7 @@ test_simde_mm512_and_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512d a; simde__m512d b; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 266.26), SIMDE_FLOAT64_C( 537.32), SIMDE_FLOAT64_C( -326.88), SIMDE_FLOAT64_C( -882.50), SIMDE_FLOAT64_C( -89.28), SIMDE_FLOAT64_C( -631.60), @@ -266,7 +266,7 @@ test_simde_mm512_mask_and_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m512 a; simde__m512 b; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -343.60), SIMDE_FLOAT32_C( -192.26), SIMDE_FLOAT32_C( -375.10), SIMDE_FLOAT32_C( 810.28), SIMDE_FLOAT32_C( -388.15), SIMDE_FLOAT32_C( 15.81), SIMDE_FLOAT32_C( 547.95), SIMDE_FLOAT32_C( 151.06), SIMDE_FLOAT32_C( -920.74), SIMDE_FLOAT32_C( -676.14), SIMDE_FLOAT32_C( -545.26), SIMDE_FLOAT32_C( -14.56), @@ -421,7 +421,7 @@ test_simde_mm512_mask_and_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512d a; simde__m512d b; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -128.09), SIMDE_FLOAT64_C( -302.68), SIMDE_FLOAT64_C( 129.66), SIMDE_FLOAT64_C( -400.28), SIMDE_FLOAT64_C( -687.60), SIMDE_FLOAT64_C( -568.06), @@ -575,7 +575,7 @@ test_simde_mm512_maskz_and_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m512 a; simde__m512 b; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(57131), simde_mm512_set_ps(SIMDE_FLOAT32_C( 399.48), SIMDE_FLOAT32_C( -238.06), SIMDE_FLOAT32_C( -893.32), SIMDE_FLOAT32_C( -435.26), SIMDE_FLOAT32_C( 522.86), SIMDE_FLOAT32_C( -612.44), SIMDE_FLOAT32_C( 652.00), SIMDE_FLOAT32_C( 895.17), @@ -697,7 +697,7 @@ test_simde_mm512_maskz_and_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512d a; simde__m512d b; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 62), simde_mm512_set_pd(SIMDE_FLOAT64_C( 337.23), SIMDE_FLOAT64_C( -706.51), SIMDE_FLOAT64_C( -51.03), SIMDE_FLOAT64_C( -11.12), @@ -818,7 +818,7 @@ test_simde_mm512_and_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( 2103907232), INT32_C(-1995421302), INT32_C( 1328084931), INT32_C( -379562245), INT32_C( 1144599747), INT32_C(-1418414219), INT32_C( 1379143176), INT32_C(-2075387410), INT32_C(-1152868472), INT32_C( 1425101887), INT32_C(-1626225579), INT32_C( 2014677400), @@ -933,7 +933,7 @@ test_simde_mm512_mask_and_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( 2103907232), INT32_C(-1995421302), INT32_C( 1328084931), INT32_C( -379562245), INT32_C( 1144599747), INT32_C(-1418414219), INT32_C( 1379143176), INT32_C(-2075387410), INT32_C(-1152868472), INT32_C( 1425101887), INT32_C(-1626225579), INT32_C( 2014677400), @@ -1087,7 +1087,7 @@ test_simde_mm512_maskz_and_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(21810), simde_mm512_set_epi32(INT32_C( 1183808039), INT32_C( 2103907232), INT32_C(-1995421302), INT32_C( 1328084931), INT32_C( -379562245), INT32_C( 1144599747), INT32_C(-1418414219), INT32_C( 1379143176), @@ -1208,7 +1208,7 @@ test_simde_mm512_and_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C( 9036212757557430666), INT64_C( 5704081348870821627), INT64_C( 4916018483251427189), INT64_C( 5923374839641151982), INT64_C(-4951532382404389825), INT64_C(-6984585675708986984), @@ -1323,7 +1323,7 @@ test_simde_mm512_mask_and_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C( 9036212757557430666), INT64_C( 5704081348870821627), INT64_C( 4916018483251427189), INT64_C( 5923374839641151982), INT64_C(-4951532382404389825), INT64_C(-6984585675708986984), @@ -1477,7 +1477,7 @@ test_simde_mm512_maskz_and_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 50), simde_mm512_set_epi64(INT64_C( 5084416814350799776), INT64_C(-8570269232503654461), INT64_C(-1630207427926739773), INT64_C(-6092042681407238648), @@ -1598,7 +1598,7 @@ test_simde_mm512_and_si512(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( 1762603276), INT32_C(-1316946536), INT32_C( -409636803), INT32_C(-1096492450), INT32_C( 1487241173), INT32_C(-1940071138), INT32_C( 1116126146), INT32_C( -916337722), INT32_C( 52488417), INT32_C( 1044081507), INT32_C(-1035184013), INT32_C(-1384518181), diff --git a/test/x86/avx512/andnot.c b/test/x86/avx512/andnot.c index 096342bd1..ad39c6dd8 100644 --- a/test/x86/avx512/andnot.c +++ b/test/x86/avx512/andnot.c @@ -37,7 +37,7 @@ test_simde_mm512_andnot_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( 515723887), INT32_C( 1640697809), INT32_C(-1815268655), INT32_C( -855842079), INT32_C( -876731021), INT32_C( -422224087), INT32_C( 1402147089), INT32_C( 791567468), INT32_C( -405953943), INT32_C( 280958773), INT32_C( 359942894), INT32_C( -574064836), @@ -150,7 +150,7 @@ test_simde_mm512_andnot_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C(-5692392796256408556), INT64_C( 6556277497990144923), INT64_C(-8451768093244871108), INT64_C( 2502789693644361692), INT64_C( 1621880469938104082), INT64_C(-7297255235572331483), @@ -265,7 +265,7 @@ test_simde_mm512_mask_andnot_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( 483765022), INT32_C(-1234873154), INT32_C(-1289658932), INT32_C( 1557667178), INT32_C( -573006378), INT32_C( -844585804), INT32_C( 908677468), INT32_C( 120945929), INT32_C(-1595338087), INT32_C(-1433288415), INT32_C( 1272415402), INT32_C( 2052605464), @@ -419,7 +419,7 @@ test_simde_mm512_maskz_andnot_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(41898), simde_mm512_set_epi32(INT32_C(-1595502197), INT32_C(-1527248547), INT32_C( 1075363080), INT32_C(-1963744626), INT32_C( -841874568), INT32_C( 1348974030), INT32_C( 932258327), INT32_C(-1638556215), @@ -542,7 +542,7 @@ test_simde_mm512_mask_andnot_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C( -343739447634695407), INT64_C( 6094193684923690615), INT64_C(-7040634603669948000), INT64_C( 8872386007247991164), INT64_C(-8252638392294099885), INT64_C( 6601029892750146432), @@ -696,7 +696,7 @@ test_simde_mm512_maskz_andnot_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C(227), simde_mm512_set_epi64(INT64_C(-4590720219282553470), INT64_C( 7052994564826635717), INT64_C( 102182550423351600), INT64_C( 6550609573293042333), @@ -817,7 +817,7 @@ test_simde_mm512_andnot_si512(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( -335330897), INT32_C( 1860840666), INT32_C( -837102383), INT32_C( 1544121603), INT32_C( -31451516), INT32_C( 294501250), INT32_C( 1844141610), INT32_C( 711066163), INT32_C( 1032767823), INT32_C( 466876164), INT32_C( 1432923079), INT32_C( -137339965), @@ -930,7 +930,7 @@ test_simde_mm512_andnot_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( 1786505147), INT32_C( 366806262), INT32_C(-1595474360), INT32_C( -741125130), INT32_C( 623580589), INT32_C( 1819639708), INT32_C(-1998267151), INT32_C( 54696203), INT32_C( 1230356730), INT32_C( -528215990), INT32_C(-1085976265), INT32_C( -88891472), @@ -1045,7 +1045,7 @@ test_simde_mm512_mask_andnot_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C(-1056724565), INT32_C( 1525326722), INT32_C( -860629095), INT32_C( 1674345138), INT32_C( -780517906), INT32_C(-1953060088), INT32_C(-1307294727), INT32_C(-1463687440), INT32_C( -675695615), INT32_C( 1308561010), INT32_C( 639253006), INT32_C( -651243687), @@ -1199,7 +1199,7 @@ test_simde_mm512_maskz_andnot_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(56303), simde_mm512_set_epi32(INT32_C( 684353163), INT32_C( -624296854), INT32_C(-1626870831), INT32_C( 1693659819), INT32_C( 1814966119), INT32_C( 1428960968), INT32_C( 1709146671), INT32_C(-1269736679), @@ -1320,7 +1320,7 @@ test_simde_mm512_andnot_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C( 207721957124820559), INT64_C( 7800065217939756514), INT64_C(-3924116943760495845), INT64_C(-4670511705337769443), INT64_C( 8681164262815197674), INT64_C(-1748050366477277388), @@ -1435,7 +1435,7 @@ test_simde_mm512_mask_andnot_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C(-8706055201876274534), INT64_C(-2974526497282267924), INT64_C(-5064099105424399850), INT64_C( 4173762680971677425), INT64_C( 5058953897646810163), INT64_C( 3129329827313761969), @@ -1589,7 +1589,7 @@ test_simde_mm512_maskz_andnot_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 7), simde_mm512_set_epi64(INT64_C(-2016264017930850215), INT64_C( 6207900603916400351), INT64_C( 7392720324711365837), INT64_C( 8770333430120422633), diff --git a/test/x86/avx512/avg.c b/test/x86/avx512/avg.c index f39ba6247..d190ab504 100644 --- a/test/x86/avx512/avg.c +++ b/test/x86/avx512/avg.c @@ -773,7 +773,7 @@ test_simde_mm512_avg_epu8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu8(UINT8_C( 54), UINT8_C( 98), UINT8_C(144), UINT8_C( 33), UINT8_C(227), UINT8_C( 68), UINT8_C( 44), UINT8_C(252), UINT8_C(188), UINT8_C(131), UINT8_C( 22), UINT8_C(137), @@ -1176,7 +1176,7 @@ test_simde_mm512_mask_avg_epu8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu8(UINT8_C(117), UINT8_C(152), UINT8_C(221), UINT8_C(216), UINT8_C(255), UINT8_C( 43), UINT8_C( 10), UINT8_C(211), UINT8_C(214), UINT8_C( 80), UINT8_C(187), UINT8_C(241), @@ -1714,7 +1714,7 @@ test_simde_mm512_maskz_avg_epu8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT64_C( 1713497089), simde_x_mm512_set_epu8(UINT8_C(151), UINT8_C( 80), UINT8_C(240), UINT8_C(132), UINT8_C(208), UINT8_C( 76), UINT8_C(165), UINT8_C(128), @@ -2123,7 +2123,7 @@ test_simde_mm512_avg_epu16(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu16(UINT16_C( 13922), UINT16_C( 36897), UINT16_C( 58180), UINT16_C( 11516), UINT16_C( 48259), UINT16_C( 5769), UINT16_C( 28390), UINT16_C( 29726), UINT16_C( 60808), UINT16_C( 38778), UINT16_C( 21386), UINT16_C( 37563), diff --git a/test/x86/avx512/blend.c b/test/x86/avx512/blend.c index 7d15a5b00..9d9fe1f93 100644 --- a/test/x86/avx512/blend.c +++ b/test/x86/avx512/blend.c @@ -1374,7 +1374,7 @@ test_simde_mm512_mask_blend_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(12684), simde_mm512_set_epi32(INT32_C( 2139597246), INT32_C(-2035467821), INT32_C(-1381016544), INT32_C( -293624181), INT32_C( 1610331725), INT32_C( 134146865), INT32_C( 837546022), INT32_C(-1561535917), @@ -1496,7 +1496,7 @@ test_simde_mm512_mask_blend_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C(140), simde_mm512_set_epi64(INT64_C(-8742267720341431264), INT64_C(-1261106253099452851), INT64_C( 576156398873473062), INT64_C(-6706745694521602474), @@ -1618,7 +1618,7 @@ test_simde_mm512_mask_blend_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m512 a; simde__m512 b; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(28658), simde_mm512_set_ps(SIMDE_FLOAT32_C( 986.64), SIMDE_FLOAT32_C( 121.90), SIMDE_FLOAT32_C( -796.62), SIMDE_FLOAT32_C( 983.17), SIMDE_FLOAT32_C( 569.02), SIMDE_FLOAT32_C( -88.58), SIMDE_FLOAT32_C( -750.53), SIMDE_FLOAT32_C( 52.16), @@ -1740,7 +1740,7 @@ test_simde_mm512_mask_blend_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512d a; simde__m512d b; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C(211), simde_mm512_set_pd(SIMDE_FLOAT64_C( 863.27), SIMDE_FLOAT64_C( -937.53), SIMDE_FLOAT64_C( 272.85), SIMDE_FLOAT64_C( -836.56), diff --git a/test/x86/avx512/broadcast.c b/test/x86/avx512/broadcast.c index 10d380a0d..b360217eb 100644 --- a/test/x86/avx512/broadcast.c +++ b/test/x86/avx512/broadcast.c @@ -1110,7 +1110,7 @@ test_simde_mm512_broadcast_f32x4(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_ps(SIMDE_FLOAT32_C( 241.63), SIMDE_FLOAT32_C( 962.32), SIMDE_FLOAT32_C( -223.53), SIMDE_FLOAT32_C( -221.69)), simde_mm512_set_ps(SIMDE_FLOAT32_C( 241.63), SIMDE_FLOAT32_C( 962.32), SIMDE_FLOAT32_C( -223.53), SIMDE_FLOAT32_C( -221.69), SIMDE_FLOAT32_C( 241.63), SIMDE_FLOAT32_C( 962.32), SIMDE_FLOAT32_C( -223.53), SIMDE_FLOAT32_C( -221.69), @@ -1168,7 +1168,7 @@ test_simde_mm512_mask_broadcast_f32x4(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m128 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -476.82), SIMDE_FLOAT32_C( 687.27), SIMDE_FLOAT32_C( 239.12), SIMDE_FLOAT32_C( -622.96), SIMDE_FLOAT32_C( 479.82), SIMDE_FLOAT32_C( -652.18), SIMDE_FLOAT32_C( 585.66), SIMDE_FLOAT32_C( -840.39), SIMDE_FLOAT32_C( -680.47), SIMDE_FLOAT32_C( -211.69), SIMDE_FLOAT32_C( 879.50), SIMDE_FLOAT32_C( 245.88), @@ -1265,7 +1265,7 @@ test_simde_mm512_maskz_broadcast_f32x4(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m128 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(12860), simde_mm_set_ps(SIMDE_FLOAT32_C( -93.71), SIMDE_FLOAT32_C( 137.99), SIMDE_FLOAT32_C( 492.43), SIMDE_FLOAT32_C( 420.83)), simde_mm512_set_ps(SIMDE_FLOAT32_C( 0.00), SIMDE_FLOAT32_C( 0.00), SIMDE_FLOAT32_C( 492.43), SIMDE_FLOAT32_C( 420.83), @@ -1329,7 +1329,7 @@ test_simde_mm512_broadcast_f64x4(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 241.63), SIMDE_FLOAT64_C( 962.32), SIMDE_FLOAT64_C( -223.53), SIMDE_FLOAT64_C( -221.69)), simde_mm512_set_pd(SIMDE_FLOAT64_C( 241.63), SIMDE_FLOAT64_C( 962.32), @@ -1395,7 +1395,7 @@ test_simde_mm512_mask_broadcast_f64x4(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m256d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -396.88), SIMDE_FLOAT64_C( 354.04), SIMDE_FLOAT64_C( 268.06), SIMDE_FLOAT64_C( -972.10), SIMDE_FLOAT64_C( -213.85), SIMDE_FLOAT64_C( -574.68), @@ -1500,7 +1500,7 @@ test_simde_mm512_maskz_broadcast_f64x4(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m256d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 25), simde_mm256_set_pd(SIMDE_FLOAT64_C( -93.71), SIMDE_FLOAT64_C( 137.99), SIMDE_FLOAT64_C( 492.43), SIMDE_FLOAT64_C( 420.83)), @@ -1572,7 +1572,7 @@ test_simde_mm512_broadcast_i32x4(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi32(INT32_C( 1322912216), INT32_C( -192131569), INT32_C( 457247766), INT32_C( 1585478853)), simde_mm512_set_epi32(INT32_C( 1322912216), INT32_C( -192131569), INT32_C( 457247766), INT32_C( 1585478853), INT32_C( 1322912216), INT32_C( -192131569), INT32_C( 457247766), INT32_C( 1585478853), @@ -1630,7 +1630,7 @@ test_simde_mm512_mask_broadcast_i32x4(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m128i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( 1479802474), INT32_C( 587294539), INT32_C( -174751528), INT32_C( 1465222154), INT32_C( 1625882140), INT32_C(-1283973275), INT32_C( 567394727), INT32_C( 1808136008), INT32_C( 324921956), INT32_C(-1888780980), INT32_C( -262803011), INT32_C( 2131227345), @@ -1727,7 +1727,7 @@ test_simde_mm512_maskz_broadcast_i32x4(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m128i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(57503), simde_mm_set_epi32(INT32_C( 913371223), INT32_C( 1946242675), INT32_C(-1851162974), INT32_C(-1090004303)), simde_mm512_set_epi32(INT32_C( 913371223), INT32_C( 1946242675), INT32_C(-1851162974), INT32_C( 0), @@ -1791,7 +1791,7 @@ test_simde_mm512_broadcast_i64x4(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C( 2067253863170152603), INT64_C( 7322969156688688496), INT64_C(-3040413397780943697), INT64_C( -347515311309491350)), simde_mm512_set_epi64(INT64_C( 2067253863170152603), INT64_C( 7322969156688688496), @@ -1857,7 +1857,7 @@ test_simde_mm512_mask_broadcast_i64x4(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m256i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C(-6314317108894035774), INT64_C( 8866317312363406147), INT64_C( 6809917121524389565), INT64_C(-3241424127607560167), INT64_C(-6106086665810303781), INT64_C( 633642393017577559), @@ -1962,7 +1962,7 @@ test_simde_mm512_maskz_broadcast_i64x4(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m256i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 81), simde_mm256_set_epi64x(INT64_C(-3226888659503117201), INT64_C( 7490209482650655404), INT64_C(-9179276487306987344), INT64_C( 7055682156038845095)), @@ -2034,7 +2034,7 @@ test_simde_mm512_broadcastd_epi32(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi32(INT32_C(-1051270324), INT32_C(-1977183446), INT32_C( -548195640), INT32_C(-1363461466)), simde_mm512_set_epi32(INT32_C(-1363461466), INT32_C(-1363461466), INT32_C(-1363461466), INT32_C(-1363461466), INT32_C(-1363461466), INT32_C(-1363461466), INT32_C(-1363461466), INT32_C(-1363461466), @@ -2092,7 +2092,7 @@ test_simde_mm512_mask_broadcastd_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m128i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( 1638944021), INT32_C( -385149059), INT32_C( 852916680), INT32_C(-1839015366), INT32_C( 1146921463), INT32_C( 765234486), INT32_C( -388218844), INT32_C(-1402803832), INT32_C( 1245942358), INT32_C( 2001202713), INT32_C( 868062804), INT32_C(-1988191751), @@ -2189,7 +2189,7 @@ test_simde_mm512_maskz_broadcastd_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m128i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(21274), simde_mm_set_epi32(INT32_C( 1459257075), INT32_C( 587801532), INT32_C( 1631678564), INT32_C( 715337051)), simde_mm512_set_epi32(INT32_C( 0), INT32_C( 715337051), INT32_C( 0), INT32_C( 715337051), @@ -2253,7 +2253,7 @@ test_simde_mm512_broadcastq_epi64(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi64x(INT64_C(-4515171658517540054), INT64_C(-2354482342678283610)), simde_mm512_set_epi64(INT64_C(-2354482342678283610), INT64_C(-2354482342678283610), INT64_C(-2354482342678283610), INT64_C(-2354482342678283610), @@ -2311,7 +2311,7 @@ test_simde_mm512_mask_broadcastq_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m128i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C( 7039210974079555453), INT64_C( 3663249249268849210), INT64_C( 4925990175430708534), INT64_C(-1667387235778762360), INT64_C( 5351281682312326681), INT64_C( 3728301356360833529), @@ -2408,7 +2408,7 @@ test_simde_mm512_maskz_broadcastq_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m128i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 26), simde_mm_set_epi64x(INT64_C( 2524588358110376036), INT64_C( 3072349241054123220)), simde_mm512_set_epi64(INT64_C( 0), INT64_C( 0), @@ -2472,7 +2472,7 @@ test_simde_mm512_broadcastss_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_ps(SIMDE_FLOAT32_C( 104.48), SIMDE_FLOAT32_C( 410.97), SIMDE_FLOAT32_C( 548.32), SIMDE_FLOAT32_C( 631.04)), simde_mm512_set_ps(SIMDE_FLOAT32_C( 631.04), SIMDE_FLOAT32_C( 631.04), SIMDE_FLOAT32_C( 631.04), SIMDE_FLOAT32_C( 631.04), SIMDE_FLOAT32_C( 631.04), SIMDE_FLOAT32_C( 631.04), SIMDE_FLOAT32_C( 631.04), SIMDE_FLOAT32_C( 631.04), @@ -2530,7 +2530,7 @@ test_simde_mm512_mask_broadcastss_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m128 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -227.30), SIMDE_FLOAT32_C( 999.04), SIMDE_FLOAT32_C( 956.07), SIMDE_FLOAT32_C( -270.40), SIMDE_FLOAT32_C( 132.00), SIMDE_FLOAT32_C( 480.19), SIMDE_FLOAT32_C( -107.97), SIMDE_FLOAT32_C( -347.00), SIMDE_FLOAT32_C( -927.52), SIMDE_FLOAT32_C( -67.87), SIMDE_FLOAT32_C( 891.86), SIMDE_FLOAT32_C( -870.50), @@ -2627,7 +2627,7 @@ test_simde_mm512_maskz_broadcastss_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m128 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(25371), simde_mm_set_ps(SIMDE_FLOAT32_C( 104.48), SIMDE_FLOAT32_C( 410.97), SIMDE_FLOAT32_C( 548.32), SIMDE_FLOAT32_C( 631.04)), simde_mm512_set_ps(SIMDE_FLOAT32_C( 0.00), SIMDE_FLOAT32_C( 631.04), SIMDE_FLOAT32_C( 631.04), SIMDE_FLOAT32_C( 0.00), @@ -2691,7 +2691,7 @@ test_simde_mm512_broadcastsd_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_pd(SIMDE_FLOAT64_C( 912.41), SIMDE_FLOAT64_C( 842.49)), simde_mm512_set_pd(SIMDE_FLOAT64_C( 842.49), SIMDE_FLOAT64_C( 842.49), SIMDE_FLOAT64_C( 842.49), SIMDE_FLOAT64_C( 842.49), @@ -2749,7 +2749,7 @@ test_simde_mm512_mask_broadcastsd_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m128d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -746.75), SIMDE_FLOAT64_C( 634.39), SIMDE_FLOAT64_C( -651.68), SIMDE_FLOAT64_C( -903.55), SIMDE_FLOAT64_C( 689.73), SIMDE_FLOAT64_C( 178.89), @@ -2846,7 +2846,7 @@ test_simde_mm512_maskz_broadcastsd_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m128d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C(128), simde_mm_set_pd(SIMDE_FLOAT64_C( 912.41), SIMDE_FLOAT64_C( 842.49)), simde_mm512_set_pd(SIMDE_FLOAT64_C( 842.49), SIMDE_FLOAT64_C( 0.00), @@ -2910,7 +2910,7 @@ test_simde_mm512_broadcastb_epi8(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi8(INT8_C( -17), INT8_C( 88), INT8_C(-122), INT8_C(-119), INT8_C( 111), INT8_C( 87), INT8_C( -76), INT8_C( 27), INT8_C( -93), INT8_C( -8), INT8_C( -17), INT8_C( 24), @@ -3088,7 +3088,7 @@ test_simde_mm512_mask_broadcastb_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__mmask64 k; simde__m128i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( 65), INT8_C( -68), INT8_C( 102), INT8_C(-122), INT8_C( 40), INT8_C( 19), INT8_C(-111), INT8_C( 8), INT8_C( -58), INT8_C(-120), INT8_C( 111), INT8_C( 10), @@ -3401,7 +3401,7 @@ test_simde_mm512_maskz_broadcastb_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__mmask64 k; simde__m128i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT64_C( 2081702095), simde_mm_set_epi8(INT8_C( 126), INT8_C( -6), INT8_C( 16), INT8_C( 102), INT8_C( -47), INT8_C(-116), INT8_C( -4), INT8_C( 33), @@ -3585,7 +3585,7 @@ test_simde_mm512_broadcastw_epi16(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi16(INT16_C( -4264), INT16_C(-31095), INT16_C( 28503), INT16_C(-19429), INT16_C(-23560), INT16_C( -4328), INT16_C( 17780), INT16_C(-19836)), simde_mm512_set_epi16(INT16_C(-19836), INT16_C(-19836), INT16_C(-19836), INT16_C(-19836), diff --git a/test/x86/avx512/cast.c b/test/x86/avx512/cast.c index 642fcd020..5513c9a8c 100644 --- a/test/x86/avx512/cast.c +++ b/test/x86/avx512/cast.c @@ -36,7 +36,7 @@ test_simde_mm512_castpd512_pd128(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512d a; simde__m128d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -503.58), SIMDE_FLOAT64_C( 409.99), SIMDE_FLOAT64_C( 882.79), SIMDE_FLOAT64_C( 967.41), SIMDE_FLOAT64_C( 644.16), SIMDE_FLOAT64_C( 22.93), @@ -92,7 +92,7 @@ test_simde_mm512_castpd512_pd256(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 414.39), SIMDE_FLOAT64_C( -15.63), SIMDE_FLOAT64_C( 546.05), SIMDE_FLOAT64_C( -960.01), SIMDE_FLOAT64_C( -752.11), SIMDE_FLOAT64_C( -702.83), @@ -156,7 +156,7 @@ test_simde_mm512_castpd128_pd512(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_pd(SIMDE_FLOAT64_C( 605.48), SIMDE_FLOAT64_C( 349.95)), simde_mm512_set_pd(SIMDE_FLOAT64_C( 0.00), SIMDE_FLOAT64_C( 0.00), SIMDE_FLOAT64_C( 0.00), SIMDE_FLOAT64_C( 0.00), @@ -213,7 +213,7 @@ test_simde_mm512_castpd256_pd512(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -610.76), SIMDE_FLOAT64_C( -445.99), SIMDE_FLOAT64_C( -292.19), SIMDE_FLOAT64_C( 327.18)), simde_mm512_set_pd(SIMDE_FLOAT64_C( 0.00), SIMDE_FLOAT64_C( 0.00), @@ -278,7 +278,7 @@ test_simde_mm512_castps512_ps128(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512 a; simde__m128 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( 764.32), SIMDE_FLOAT32_C( -951.31), SIMDE_FLOAT32_C( 179.06), SIMDE_FLOAT32_C( -437.66), SIMDE_FLOAT32_C( 402.64), SIMDE_FLOAT32_C( 734.29), SIMDE_FLOAT32_C( 267.34), SIMDE_FLOAT32_C( 208.00), SIMDE_FLOAT32_C( 587.55), SIMDE_FLOAT32_C( -635.96), SIMDE_FLOAT32_C( -958.84), SIMDE_FLOAT32_C( -271.31), @@ -334,7 +334,7 @@ test_simde_mm512_castps512_ps256(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( 516.61), SIMDE_FLOAT32_C( 494.30), SIMDE_FLOAT32_C( 266.21), SIMDE_FLOAT32_C( 450.63), SIMDE_FLOAT32_C( -862.95), SIMDE_FLOAT32_C( -528.18), SIMDE_FLOAT32_C( 206.23), SIMDE_FLOAT32_C( -212.40), SIMDE_FLOAT32_C( 805.40), SIMDE_FLOAT32_C( -902.72), SIMDE_FLOAT32_C( -631.10), SIMDE_FLOAT32_C( -480.24), @@ -414,7 +414,7 @@ test_simde_mm512_castps_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -475.09), SIMDE_FLOAT32_C( 736.84), SIMDE_FLOAT32_C( -702.97), SIMDE_FLOAT32_C( -433.94), SIMDE_FLOAT32_C( 854.93), SIMDE_FLOAT32_C( -157.11), SIMDE_FLOAT32_C( 43.61), SIMDE_FLOAT32_C( -310.79), SIMDE_FLOAT32_C( -893.63), SIMDE_FLOAT32_C( 37.00), SIMDE_FLOAT32_C( 245.96), SIMDE_FLOAT32_C( 381.92), @@ -493,7 +493,7 @@ test_simde_mm512_castsi512_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( 1318886849), INT32_C( -963615992), INT32_C( 1168255165), INT32_C(-1910220907), INT32_C( -362848940), INT32_C( 1228894571), INT32_C( -604141281), INT32_C( -310556576), INT32_C( -195291453), INT32_C(-1762187610), INT32_C( 785462248), INT32_C(-1654799886), @@ -633,7 +633,7 @@ test_simde_mm512_castpd_si512(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C(-2932283473482861325), INT64_C(-7551244776617231168), INT64_C(-7807931705287408960), INT64_C(-5709657210396534887), INT64_C(-5733822187822983321), INT64_C(-6449026762131886574), @@ -713,7 +713,7 @@ test_simde_mm512_castsi512_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C(-2932283473482861325), INT64_C(-7551244776617231168), INT64_C(-7807931705287408960), INT64_C(-5709657210396534887), INT64_C(-5733822187822983321), INT64_C(-6449026762131886574), @@ -793,7 +793,7 @@ test_simde_mm512_castsi128_si512(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi32(INT32_C(-1668834023), INT32_C(-1352312258), INT32_C( 556637397), INT32_C( -245835434)), simde_mm512_set_epi32(INT32_C( 0), INT32_C( 0), INT32_C( 0), INT32_C( 0), INT32_C( 0), INT32_C( 0), INT32_C( 0), INT32_C( 0), @@ -850,7 +850,7 @@ test_simde_mm512_castsi256_si512(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( -627018310), INT32_C( -732773372), INT32_C(-1935004141), INT32_C( 1864732488), INT32_C( 140289699), INT32_C(-1570899663), INT32_C(-1630998993), INT32_C( 818347323)), simde_mm512_set_epi32(INT32_C( 0), INT32_C( 0), INT32_C( 0), INT32_C( 0), @@ -915,7 +915,7 @@ test_simde_mm512_castps_si512(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( 1318886849), INT32_C( -963615992), INT32_C( 1168255165), INT32_C(-1910220907), INT32_C( -362848940), INT32_C( 1228894571), INT32_C( -604141281), INT32_C( -310556576), INT32_C( -195291453), INT32_C(-1762187610), INT32_C( 785462248), INT32_C(-1654799886), @@ -995,7 +995,7 @@ test_simde_mm512_castps128_ps512(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m128 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_ps(SIMDE_FLOAT32_C( -124.41), SIMDE_FLOAT32_C( 994.42), SIMDE_FLOAT32_C( -888.56), SIMDE_FLOAT32_C( -241.67)), simde_mm512_set_ps(SIMDE_FLOAT32_C( 0.00), SIMDE_FLOAT32_C( 0.00), SIMDE_FLOAT32_C( 0.00), SIMDE_FLOAT32_C( 0.00), SIMDE_FLOAT32_C( 0.00), SIMDE_FLOAT32_C( 0.00), SIMDE_FLOAT32_C( 0.00), SIMDE_FLOAT32_C( 0.00), @@ -1052,7 +1052,7 @@ test_simde_mm512_castps256_ps512(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( -144.51), SIMDE_FLOAT32_C( 522.85), SIMDE_FLOAT32_C( 259.94), SIMDE_FLOAT32_C( 889.02), SIMDE_FLOAT32_C( 47.86), SIMDE_FLOAT32_C( 181.02), @@ -1133,7 +1133,7 @@ test_simde_mm512_castsi512_si128(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512i a; simde__m128i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( 1658575222), INT32_C(-1117261553), INT32_C(-1839997259), INT32_C( -299852262), INT32_C( -856912374), INT32_C( 2142936567), INT32_C( -954684084), INT32_C( 1657017766), INT32_C( -348123015), INT32_C( -101609698), INT32_C( 554693435), INT32_C(-1533582435), @@ -1189,7 +1189,7 @@ test_simde_mm512_castsi512_si256(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( 1313023361), INT32_C( -284143420), INT32_C( 762022716), INT32_C( -109476439), INT32_C( -377196873), INT32_C( 289021876), INT32_C(-1835156104), INT32_C(-2032178077), INT32_C(-1821500948), INT32_C( 676317044), INT32_C( 1400280404), INT32_C(-1176819357), diff --git a/test/x86/avx512/cmpeq.c b/test/x86/avx512/cmpeq.c index 01e74412e..28b30c229 100644 --- a/test/x86/avx512/cmpeq.c +++ b/test/x86/avx512/cmpeq.c @@ -37,7 +37,7 @@ test_simde_mm512_cmpeq_epi8_mask(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__mmask64 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( 73), INT8_C( 68), INT8_C( -71), INT8_C( -32), INT8_C( 100), INT8_C( 125), INT8_C( 89), INT8_C( 95), INT8_C( -23), INT8_C( 76), INT8_C( 84), INT8_C( -43), @@ -318,7 +318,7 @@ test_simde_mm512_cmpeq_epi32_mask(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__mmask16 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( 1955445938), INT32_C( 1791143901), INT32_C(-1554982337), INT32_C(-1864115653), INT32_C(-1774796435), INT32_C( 1168347531), INT32_C( 660969508), INT32_C( 1153796239), INT32_C( 609464964), INT32_C( 1687040663), INT32_C( -477087011), INT32_C( 309017072), @@ -408,7 +408,7 @@ test_simde_mm512_mask_cmpeq_epi32_mask(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__mmask16 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(15798), simde_mm512_set_epi32(INT32_C(-1396783922), INT32_C( 2147469122), INT32_C( 245941047), INT32_C(-1608794680), INT32_C( 1508622706), INT32_C( -820009589), INT32_C(-2056933337), INT32_C( 1399160559), @@ -505,7 +505,7 @@ test_simde_mm512_cmpeq_epi64_mask(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__mmask8 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C( 1145569124203592220), INT64_C( 8866992319046943109), INT64_C( 1920152028348566704), INT64_C( 5434169962120345100), INT64_C( 2279810443797316081), INT64_C( 8202334326145056493), @@ -595,7 +595,7 @@ test_simde_mm512_mask_cmpeq_epi64_mask(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__mmask8 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 90), simde_mm512_set_epi64(INT64_C( 7722926897436765530), INT64_C( 7338279138551748064), INT64_C( 8433308126101200079), INT64_C(-4390305748733976547), diff --git a/test/x86/avx512/cmpge.c b/test/x86/avx512/cmpge.c index 5564ff4a5..cbea10c12 100644 --- a/test/x86/avx512/cmpge.c +++ b/test/x86/avx512/cmpge.c @@ -37,7 +37,7 @@ test_simde_mm512_cmpge_epi8_mask(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__mmask64 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( 92), INT8_C(-121), INT8_C( 120), INT8_C( -19), INT8_C( -73), INT8_C( 22), INT8_C( -66), INT8_C( -29), INT8_C( 55), INT8_C( -63), INT8_C( -45), INT8_C(-119), @@ -318,7 +318,7 @@ test_simde_mm512_cmpge_epu8_mask(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__mmask64 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu8(UINT8_C( 92), UINT8_C(135), UINT8_C(120), UINT8_C(237), UINT8_C(183), UINT8_C( 22), UINT8_C(190), UINT8_C(227), UINT8_C( 55), UINT8_C(193), UINT8_C(211), UINT8_C(137), diff --git a/test/x86/avx512/cmpgt.c b/test/x86/avx512/cmpgt.c index 12ca768b7..175b4a851 100644 --- a/test/x86/avx512/cmpgt.c +++ b/test/x86/avx512/cmpgt.c @@ -37,7 +37,7 @@ test_simde_mm512_cmpgt_epi8_mask(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__mmask64 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( 92), INT8_C(-121), INT8_C( 120), INT8_C( -19), INT8_C( -73), INT8_C( 22), INT8_C( -66), INT8_C( -29), INT8_C( 55), INT8_C( -63), INT8_C( -45), INT8_C(-119), @@ -318,7 +318,7 @@ test_simde_mm512_cmpgt_epu8_mask(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__mmask64 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu8(UINT8_C( 92), UINT8_C(135), UINT8_C(120), UINT8_C(237), UINT8_C(183), UINT8_C( 22), UINT8_C(190), UINT8_C(227), UINT8_C( 55), UINT8_C(193), UINT8_C(211), UINT8_C(137), @@ -599,7 +599,7 @@ test_simde_mm512_cmpgt_epi32_mask(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__mmask16 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( -126651070), INT32_C( 1757388710), INT32_C( 617530196), INT32_C( 407807901), INT32_C( 1271989524), INT32_C( 1251214807), INT32_C(-1247045111), INT32_C(-1024057759), INT32_C( 50729453), INT32_C( 464444874), INT32_C( 1840702207), INT32_C( 1916050591), @@ -689,7 +689,7 @@ test_simde_mm512_mask_cmpgt_epi32_mask(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__mmask16 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(12249), simde_mm512_set_epi32(INT32_C(-1151856667), INT32_C( -49918748), INT32_C(-1709830250), INT32_C( 1750293451), INT32_C(-1728641738), INT32_C( 79295022), INT32_C( 308064941), INT32_C( 1216157597), @@ -786,7 +786,7 @@ test_simde_mm512_cmpgt_epi64_mask(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__mmask8 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C(-3344943500899736927), INT64_C( -508674271294480923), INT64_C( 4367550852745697236), INT64_C(-1765523250257788813), INT64_C(-6325172456788566604), INT64_C( 3340966423446181237), @@ -876,7 +876,7 @@ test_simde_mm512_mask_cmpgt_epi64_mask(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__mmask8 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 16), simde_mm512_set_epi64(INT64_C( 2255026789087372129), INT64_C( 6954636019969939696), INT64_C( 8135587588110756767), INT64_C(-6775895683000468083), diff --git a/test/x86/avx512/cmple.c b/test/x86/avx512/cmple.c index b23ce02a6..9e25fab4d 100644 --- a/test/x86/avx512/cmple.c +++ b/test/x86/avx512/cmple.c @@ -36,7 +36,7 @@ test_simde_mm512_cmple_epi8_mask(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__mmask64 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( 52), INT8_C( 1), INT8_C( 13), INT8_C( 75), INT8_C( -85), INT8_C( 72), INT8_C( -19), INT8_C( -45), INT8_C( -9), INT8_C(-112), INT8_C( -83), INT8_C( -75), @@ -317,7 +317,7 @@ test_simde_mm512_cmple_epu8_mask(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__mmask64 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu8(UINT8_C(212), UINT8_C( 13), UINT8_C( 31), UINT8_C(214), UINT8_C(180), UINT8_C(244), UINT8_C( 71), UINT8_C( 63), UINT8_C(225), UINT8_C(144), UINT8_C( 44), UINT8_C(106), diff --git a/test/x86/avx512/cmplt.c b/test/x86/avx512/cmplt.c index 26e2b5cc4..b939e5280 100644 --- a/test/x86/avx512/cmplt.c +++ b/test/x86/avx512/cmplt.c @@ -36,7 +36,7 @@ test_simde_mm512_cmplt_epi8_mask(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__mmask64 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( -77), INT8_C( -25), INT8_C( -46), INT8_C( 46), INT8_C( 13), INT8_C( 4), INT8_C( -85), INT8_C( -85), INT8_C( -84), INT8_C( -54), INT8_C( 24), INT8_C( 27), @@ -317,7 +317,7 @@ test_simde_mm512_cmplt_epu8_mask(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__mmask64 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu8(UINT8_C(200), UINT8_C( 64), UINT8_C(228), UINT8_C(187), UINT8_C( 53), UINT8_C(115), UINT8_C(212), UINT8_C(224), UINT8_C(234), UINT8_C( 45), UINT8_C(183), UINT8_C(185), diff --git a/test/x86/avx512/cvt.c b/test/x86/avx512/cvt.c index d9698d22e..90971331c 100644 --- a/test/x86/avx512/cvt.c +++ b/test/x86/avx512/cvt.c @@ -37,7 +37,7 @@ test_simde_mm512_cvtepi16_epi8(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi16(INT16_C( 14423), INT16_C( 3775), INT16_C( 16156), INT16_C( 17811), INT16_C(-14881), INT16_C(-30283), INT16_C( 27295), INT16_C(-12290), INT16_C( 12394), INT16_C( 32764), INT16_C( 8681), INT16_C( 21255), @@ -183,7 +183,7 @@ test_simde_mm512_mask_cvtepi16_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__mmask32 k; simde__m512i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C(-112), INT8_C( 50), INT8_C( -90), INT8_C( -47), INT8_C( 24), INT8_C( -14), INT8_C( -76), INT8_C( -4), INT8_C(-104), INT8_C( 115), INT8_C( -75), INT8_C( 98), @@ -400,7 +400,7 @@ test_simde_mm512_maskz_cvtepi16_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__mmask32 k; simde__m512i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT32_C( 25439), simde_mm512_set_epi16(INT16_C( 26140), INT16_C( -8634), INT16_C( 26242), INT16_C( 1035), INT16_C(-29578), INT16_C( -2997), INT16_C( 22546), INT16_C(-28782), @@ -552,7 +552,7 @@ test_simde_mm512_cvtepi8_epi16(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C( 7), INT8_C( 68), INT8_C( -86), INT8_C( -36), INT8_C( -19), INT8_C( 73), INT8_C( 92), INT8_C( -27), INT8_C( 55), INT8_C( -65), INT8_C( -50), INT8_C( 19), diff --git a/test/x86/avx512/cvts.c b/test/x86/avx512/cvts.c index d40e5f8e0..31a275e62 100644 --- a/test/x86/avx512/cvts.c +++ b/test/x86/avx512/cvts.c @@ -101,7 +101,7 @@ test_simde_mm256_cvtsepi16_epi8(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m128i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi16(INT16_C( 447), INT16_C( -3887), INT16_C( 9), INT16_C( 6277), INT16_C( 2), INT16_C( -314), INT16_C( 1617), INT16_C( 64), INT16_C( 0), INT16_C( 1725), INT16_C( 801), INT16_C( -2), @@ -237,7 +237,7 @@ test_simde_mm256_cvtsepi32_epi8(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m128i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( 1740492550), INT32_C( 140736582), INT32_C( -304624647), INT32_C( 1856868246), INT32_C(-1035207889), INT32_C( -259975534), INT32_C( 927209588), INT32_C( -783560978)), simde_mm_set_epi8(INT8_C( 0), INT8_C( 0), INT8_C( 0), INT8_C( 0), @@ -341,7 +341,7 @@ test_simde_mm256_cvtsepi32_epi16(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m128i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( 293632982), INT32_C( -353952507), INT32_C( -369979604), INT32_C(-1836849217), INT32_C( -251503260), INT32_C(-1183044723), INT32_C(-1145018690), INT32_C( 1658446911)), simde_mm_set_epi16(INT16_C( 32767), INT16_C(-32768), INT16_C(-32768), INT16_C(-32768), @@ -445,7 +445,7 @@ test_simde_mm256_cvtsepi64_epi8(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256i a; simde__m128i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C( 7571764882458171438), INT64_C(-5921591509803744983), INT64_C( 6658090239555345361), INT64_C(-2357401607469764832)), simde_mm_set_epi8(INT8_C( 0), INT8_C( 0), INT8_C( 0), INT8_C( 0), @@ -509,7 +509,7 @@ test_simde_mm512_cvtsepi16_epi8(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi16(INT16_C( 8002), INT16_C( -42), INT16_C( 317), INT16_C( 3), INT16_C( 2), INT16_C( 22), INT16_C( 2), INT16_C( 102), INT16_C( 0), INT16_C( 130), INT16_C( 297), INT16_C( 4068), @@ -655,7 +655,7 @@ test_simde_mm512_mask_cvtsepi16_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__mmask32 k; simde__m512i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C( -40), INT8_C( 93), INT8_C( -64), INT8_C( 127), INT8_C(-121), INT8_C( -33), INT8_C( -51), INT8_C( 86), INT8_C(-123), INT8_C(-117), INT8_C(-108), INT8_C( -18), @@ -872,7 +872,7 @@ test_simde_mm512_maskz_cvtsepi16_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__mmask32 k; simde__m512i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT32_C( 16184841), simde_mm512_set_epi16(INT16_C( 26453), INT16_C(-25565), INT16_C(-27471), INT16_C(-25692), INT16_C( 24633), INT16_C(-12996), INT16_C( -7464), INT16_C( 6163), @@ -1024,7 +1024,7 @@ test_simde_mm512_cvtsepi32_epi8(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512i a; simde__m128i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( 699026811), INT32_C( -375318237), INT32_C( 900674930), INT32_C( -532379219), INT32_C( 259624037), INT32_C( -680802854), INT32_C( 1547540196), INT32_C( -396867814), INT32_C( -680186334), INT32_C( -646546417), INT32_C( 1050185959), INT32_C( 210164141), @@ -1106,7 +1106,7 @@ test_simde_mm512_mask_cvtsepi32_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512i a; simde__m128i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi8(INT8_C( 4), INT8_C( 110), INT8_C( 8), INT8_C( 124), INT8_C( -85), INT8_C( -65), INT8_C( -62), INT8_C(-114), INT8_C( 110), INT8_C( 33), INT8_C( -28), INT8_C( 106), @@ -1227,7 +1227,7 @@ test_simde_mm512_maskz_cvtsepi32_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512i a; simde__m128i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(22908), simde_mm512_set_epi32(INT32_C( 760893683), INT32_C(-2027734617), INT32_C( 1683947105), INT32_C( -424320007), INT32_C( 107722959), INT32_C( -13745640), INT32_C(-1276316442), INT32_C(-1722135079), @@ -1315,7 +1315,7 @@ test_simde_mm512_cvtsepi32_epi16(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( -633826313), INT32_C( -624858207), INT32_C( 1490386470), INT32_C(-2098903851), INT32_C(-1539984349), INT32_C( 1958536651), INT32_C(-1468703883), INT32_C( -330293651), INT32_C( 2111698546), INT32_C(-1712476271), INT32_C( 1928035775), INT32_C( 815855626), @@ -1397,7 +1397,7 @@ test_simde_mm512_mask_cvtsepi32_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi16(INT16_C( 4055), INT16_C(-20252), INT16_C(-20899), INT16_C( 32293), INT16_C( -9133), INT16_C( 17590), INT16_C( 23336), INT16_C( 12710), INT16_C( 1134), INT16_C( 2172), INT16_C(-21569), INT16_C(-15730), @@ -1518,7 +1518,7 @@ test_simde_mm512_maskz_cvtsepi32_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(22908), simde_mm512_set_epi32(INT32_C( 760893683), INT32_C(-2027734617), INT32_C( 1683947105), INT32_C( -424320007), INT32_C( 107722959), INT32_C( -13745640), INT32_C(-1276316442), INT32_C(-1722135079), @@ -1606,7 +1606,7 @@ test_simde_mm512_cvtsepi64_epi8(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512i a; simde__m128i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C( 5688878986790062607), INT64_C( -507006338933993777), INT64_C( 2731700857838766689), INT64_C( 5038766546414012764), INT64_C( 8031668245477288096), INT64_C( 8558843731862564067), @@ -1688,7 +1688,7 @@ test_simde_mm512_mask_cvtsepi64_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512i a; simde__m128i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi8(INT8_C( -98), INT8_C(-118), INT8_C( -55), INT8_C( 84), INT8_C( -38), INT8_C(-100), INT8_C( 69), INT8_C( -11), INT8_C( -76), INT8_C( -44), INT8_C( 111), INT8_C( 57), @@ -1809,7 +1809,7 @@ test_simde_mm512_maskz_cvtsepi64_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512i a; simde__m128i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 99), simde_mm512_set_epi64(INT64_C(-6773163771856001287), INT64_C( 8528895860955669022), INT64_C( 743395091751495893), INT64_C(-5753646205421077345), @@ -1897,7 +1897,7 @@ test_simde_mm512_cvtsepi64_epi16(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512i a; simde__m128i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C(-2030970610590957423), INT64_C(-6407881172688895992), INT64_C( 5763311992085393311), INT64_C( 5413217893862876377), INT64_C( 2736248102150189299), INT64_C(-3905239043220002295), @@ -1963,7 +1963,7 @@ test_simde_mm512_mask_cvtsepi64_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512i a; simde__m128i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi16(INT16_C(-24950), INT16_C(-13996), INT16_C( -9572), INT16_C( 17909), INT16_C(-19244), INT16_C( 28473), INT16_C(-27531), INT16_C(-23965)), UINT8_C( 89), @@ -2052,7 +2052,7 @@ test_simde_mm512_maskz_cvtsepi64_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512i a; simde__m128i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 99), simde_mm512_set_epi64(INT64_C(-6773163771856001287), INT64_C( 8528895860955669022), INT64_C( 743395091751495893), INT64_C(-5753646205421077345), @@ -2124,7 +2124,7 @@ test_simde_mm512_cvtsepi64_epi32(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C( -1385298216494496), INT64_C( -996445051636), INT64_C( 3207004), INT64_C( -651667828674554), INT64_C( -3476602607657036), INT64_C( -4627787), @@ -2190,7 +2190,7 @@ test_simde_mm512_mask_cvtsepi64_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( -783872818), INT32_C( 224826276), INT32_C( 833953142), INT32_C( 704393899), INT32_C(-1282792525), INT32_C(-1682931810), INT32_C( 1715663188), INT32_C(-1736532826)), UINT8_C(184), @@ -2279,7 +2279,7 @@ test_simde_mm512_maskz_cvtsepi64_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C(166), simde_mm512_set_epi64(INT64_C(-8094918606566868518), INT64_C( 4039990350021559518), INT64_C(-5079608809355355713), INT64_C( 4544449552448075830), diff --git a/test/x86/avx512/div.c b/test/x86/avx512/div.c index baea893d3..341ad5b46 100644 --- a/test/x86/avx512/div.c +++ b/test/x86/avx512/div.c @@ -38,7 +38,7 @@ test_simde_mm512_div_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m512 a; simde__m512 b; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( 653.62), SIMDE_FLOAT32_C( 981.74), SIMDE_FLOAT32_C( 780.10), SIMDE_FLOAT32_C( 59.38), SIMDE_FLOAT32_C( -795.11), SIMDE_FLOAT32_C( 923.87), SIMDE_FLOAT32_C( -270.01), SIMDE_FLOAT32_C( -411.99), SIMDE_FLOAT32_C( -97.83), SIMDE_FLOAT32_C( -393.82), SIMDE_FLOAT32_C( 934.81), SIMDE_FLOAT32_C( 74.53), @@ -153,7 +153,7 @@ test_simde_mm512_mask_div_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m512 a; simde__m512 b; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -745.89), SIMDE_FLOAT32_C( 663.97), SIMDE_FLOAT32_C( 886.69), SIMDE_FLOAT32_C( -271.39), SIMDE_FLOAT32_C( 845.36), SIMDE_FLOAT32_C( -391.34), SIMDE_FLOAT32_C( -606.86), SIMDE_FLOAT32_C( 818.59), SIMDE_FLOAT32_C( 953.36), SIMDE_FLOAT32_C( 863.40), SIMDE_FLOAT32_C( 241.85), SIMDE_FLOAT32_C( -815.86), @@ -307,7 +307,7 @@ test_simde_mm512_maskz_div_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m512 a; simde__m512 b; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(32824), simde_mm512_set_ps(SIMDE_FLOAT32_C( 745.69), SIMDE_FLOAT32_C( -258.59), SIMDE_FLOAT32_C( -549.06), SIMDE_FLOAT32_C( 646.98), SIMDE_FLOAT32_C( 925.86), SIMDE_FLOAT32_C( 378.90), SIMDE_FLOAT32_C( -524.10), SIMDE_FLOAT32_C( -563.31), @@ -428,7 +428,7 @@ test_simde_mm512_div_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512d a; simde__m512d b; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -97.83), SIMDE_FLOAT64_C( -393.82), SIMDE_FLOAT64_C( 934.81), SIMDE_FLOAT64_C( 74.53), SIMDE_FLOAT64_C( 843.79), SIMDE_FLOAT64_C( 465.05), @@ -543,7 +543,7 @@ test_simde_mm512_mask_div_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512d a; simde__m512d b; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -962.94), SIMDE_FLOAT64_C( 989.45), SIMDE_FLOAT64_C( -190.71), SIMDE_FLOAT64_C( -80.90), SIMDE_FLOAT64_C( -820.03), SIMDE_FLOAT64_C( 710.84), @@ -697,7 +697,7 @@ test_simde_mm512_maskz_div_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512d a; simde__m512d b; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C(113), simde_mm512_set_pd(SIMDE_FLOAT64_C( 112.08), SIMDE_FLOAT64_C( 712.48), SIMDE_FLOAT64_C( -754.71), SIMDE_FLOAT64_C( 256.61), diff --git a/test/x86/avx512/extract.c b/test/x86/avx512/extract.c index caa4fcde2..1a2afc60a 100644 --- a/test/x86/avx512/extract.c +++ b/test/x86/avx512/extract.c @@ -39,7 +39,7 @@ test_simde_mm512_extractf32x4_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m128 r1; simde__m128 r2; simde__m128 r3; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -563.83), SIMDE_FLOAT32_C( 799.30), SIMDE_FLOAT32_C( 938.85), SIMDE_FLOAT32_C( -576.01), SIMDE_FLOAT32_C( -465.05), SIMDE_FLOAT32_C( 439.15), SIMDE_FLOAT32_C( -104.57), SIMDE_FLOAT32_C( -28.15), SIMDE_FLOAT32_C( -431.26), SIMDE_FLOAT32_C( 481.25), SIMDE_FLOAT32_C( -57.75), SIMDE_FLOAT32_C( -784.26), @@ -131,7 +131,7 @@ test_simde_mm512_mask_extractf32x4_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m128 r1; simde__m128 r2; simde__m128 r3; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_ps(SIMDE_FLOAT32_C( -172.36), SIMDE_FLOAT32_C( 393.53), SIMDE_FLOAT32_C( 36.69), SIMDE_FLOAT32_C( -135.52)), UINT8_C( 25), simde_mm512_set_ps(SIMDE_FLOAT32_C( 903.50), SIMDE_FLOAT32_C( -43.35), SIMDE_FLOAT32_C( 309.91), SIMDE_FLOAT32_C( 846.15), @@ -238,7 +238,7 @@ test_simde_mm512_maskz_extractf32x4_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m128 r1; simde__m128 r2; simde__m128 r3; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 63), simde_mm512_set_ps(SIMDE_FLOAT32_C( 522.06), SIMDE_FLOAT32_C( 160.98), SIMDE_FLOAT32_C( -932.28), SIMDE_FLOAT32_C( 391.82), SIMDE_FLOAT32_C( 600.12), SIMDE_FLOAT32_C( -569.99), SIMDE_FLOAT32_C( -491.12), SIMDE_FLOAT32_C( -327.63), @@ -334,7 +334,7 @@ test_simde_mm512_extractf64x4_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512d a; simde__m256d r0; simde__m256d r1; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -431.26), SIMDE_FLOAT64_C( 481.25), SIMDE_FLOAT64_C( -57.75), SIMDE_FLOAT64_C( -784.26), SIMDE_FLOAT64_C( 438.04), SIMDE_FLOAT64_C( 549.03), @@ -420,7 +420,7 @@ test_simde_mm512_mask_extractf64x4_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512d a; simde__m256d r0; simde__m256d r1; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -172.36), SIMDE_FLOAT64_C( 393.53), SIMDE_FLOAT64_C( 36.69), SIMDE_FLOAT64_C( -135.52)), UINT8_C( 63), @@ -529,7 +529,7 @@ test_simde_mm512_maskz_extractf64x4_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512d a; simde__m256d r0; simde__m256d r1; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 21), simde_mm512_set_pd(SIMDE_FLOAT64_C( -139.11), SIMDE_FLOAT64_C( -172.36), SIMDE_FLOAT64_C( -268.86), SIMDE_FLOAT64_C( 393.53), @@ -623,7 +623,7 @@ test_simde_mm512_extracti32x4_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m128i r1; simde__m128i r2; simde__m128i r3; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( 936676195), INT32_C( -430989686), INT32_C( -131327474), INT32_C( 910508384), INT32_C( 1148801293), INT32_C(-1204409147), INT32_C( 1922921929), INT32_C( 2087027240), INT32_C( 1221368626), INT32_C(-1114006136), INT32_C( 2023469730), INT32_C( 463308257), @@ -715,7 +715,7 @@ test_simde_mm512_mask_extracti32x4_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m128i r1; simde__m128i r2; simde__m128i r3; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm_set_epi32(INT32_C( 1993455974), INT32_C(-2068684593), INT32_C(-1936012201), INT32_C( 1856459607)), UINT8_C( 6), simde_mm512_set_epi32(INT32_C(-1630396605), INT32_C( 1545554432), INT32_C( 344023940), INT32_C(-1871515754), @@ -822,7 +822,7 @@ test_simde_mm512_maskz_extracti32x4_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m128i r1; simde__m128i r2; simde__m128i r3; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 87), simde_mm512_set_epi32(INT32_C( 951544639), INT32_C(-1026363374), INT32_C(-1801776439), INT32_C( 145438126), INT32_C(-1306064352), INT32_C( -858736392), INT32_C( 923442479), INT32_C( 1092805562), @@ -918,7 +918,7 @@ test_simde_mm512_extracti64x4_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m256i r0; simde__m256i r1; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C( 4022993628330696330), INT64_C( -564047204985781920), INT64_C( 4934063986128071877), INT64_C( 8258886799903261224), INT64_C( 5245738308211416456), INT64_C( 8690736315259258337), @@ -1004,7 +1004,7 @@ test_simde_mm512_mask_extracti64x4_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m256i r0; simde__m256i r1; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C( 7940316924786767481), INT64_C( 6743600876828439814), INT64_C( 8561828216572109007), INT64_C(-8315109086095518889)), UINT8_C( 21), @@ -1113,7 +1113,7 @@ test_simde_mm512_maskz_extracti64x4_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m256i r0; simde__m256i r1; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 87), simde_mm512_set_epi64(INT64_C( 4086853108457730066), INT64_C(-7738570880062900818), INT64_C(-5609503674875201288), INT64_C( 3966155248134972346), diff --git a/test/x86/avx512/insert.c b/test/x86/avx512/insert.c index 81aea5ec6..585fb1917 100644 --- a/test/x86/avx512/insert.c +++ b/test/x86/avx512/insert.c @@ -40,7 +40,7 @@ test_simde_mm512_insertf32x4(SIMDE_MUNIT_TEST_ARGS) { simde__m512 r1; simde__m512 r2; simde__m512 r3; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -563.83), SIMDE_FLOAT32_C( 799.30), SIMDE_FLOAT32_C( 938.85), SIMDE_FLOAT32_C( -576.01), SIMDE_FLOAT32_C( -465.05), SIMDE_FLOAT32_C( 439.15), SIMDE_FLOAT32_C( -104.57), SIMDE_FLOAT32_C( -28.15), SIMDE_FLOAT32_C( -431.26), SIMDE_FLOAT32_C( 481.25), SIMDE_FLOAT32_C( -57.75), SIMDE_FLOAT32_C( -784.26), @@ -237,7 +237,7 @@ test_simde_mm512_mask_insertf32x4(SIMDE_MUNIT_TEST_ARGS) { simde__m512 r1; simde__m512 r2; simde__m512 r3; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( 903.50), SIMDE_FLOAT32_C( -43.35), SIMDE_FLOAT32_C( 309.91), SIMDE_FLOAT32_C( 846.15), SIMDE_FLOAT32_C( -514.56), SIMDE_FLOAT32_C( -860.98), SIMDE_FLOAT32_C( -280.30), SIMDE_FLOAT32_C( 128.51), SIMDE_FLOAT32_C( 522.06), SIMDE_FLOAT32_C( -932.28), SIMDE_FLOAT32_C( 600.12), SIMDE_FLOAT32_C( -491.12), @@ -473,7 +473,7 @@ test_simde_mm512_maskz_insertf32x4(SIMDE_MUNIT_TEST_ARGS) { simde__m512 r1; simde__m512 r2; simde__m512 r3; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(21335), simde_mm512_set_ps(SIMDE_FLOAT32_C( -556.90), SIMDE_FLOAT32_C( 522.06), SIMDE_FLOAT32_C( 160.98), SIMDE_FLOAT32_C( -932.28), SIMDE_FLOAT32_C( 391.82), SIMDE_FLOAT32_C( 600.12), SIMDE_FLOAT32_C( -569.99), SIMDE_FLOAT32_C( -491.12), @@ -674,7 +674,7 @@ test_simde_mm512_insertf64x4(SIMDE_MUNIT_TEST_ARGS) { simde__m256d b; simde__m512d r0; simde__m512d r1; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -431.26), SIMDE_FLOAT64_C( 481.25), SIMDE_FLOAT64_C( -57.75), SIMDE_FLOAT64_C( -784.26), SIMDE_FLOAT64_C( 438.04), SIMDE_FLOAT64_C( 549.03), @@ -809,7 +809,7 @@ test_simde_mm512_mask_insertf64x4(SIMDE_MUNIT_TEST_ARGS) { simde__m256d b; simde__m512d r0; simde__m512d r1; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 160.98), SIMDE_FLOAT64_C( -932.28), SIMDE_FLOAT64_C( -569.99), SIMDE_FLOAT64_C( -327.63), SIMDE_FLOAT64_C( -172.36), SIMDE_FLOAT64_C( 393.53), @@ -983,7 +983,7 @@ test_simde_mm512_maskz_insertf64x4(SIMDE_MUNIT_TEST_ARGS) { simde__m256d b; simde__m512d r0; simde__m512d r1; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 32), simde_mm512_set_pd(SIMDE_FLOAT64_C( -139.11), SIMDE_FLOAT64_C( -172.36), SIMDE_FLOAT64_C( -268.86), SIMDE_FLOAT64_C( 393.53), @@ -1126,7 +1126,7 @@ test_simde_mm512_inserti32x4(SIMDE_MUNIT_TEST_ARGS) { simde__m512i r1; simde__m512i r2; simde__m512i r3; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C(-1026363374), INT32_C(-1801776439), INT32_C( 145438126), INT32_C(-1306064352), INT32_C( -858736392), INT32_C( 923442479), INT32_C( 1092805562), INT32_C( 1443901717), INT32_C( 1848749100), INT32_C( 1777333881), INT32_C( 1570116932), INT32_C(-1302383354), @@ -1323,7 +1323,7 @@ test_simde_mm512_mask_inserti32x4(SIMDE_MUNIT_TEST_ARGS) { simde__m512i r1; simde__m512i r2; simde__m512i r3; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C(-1026363374), INT32_C(-1801776439), INT32_C( 145438126), INT32_C(-1306064352), INT32_C( -858736392), INT32_C( 923442479), INT32_C( 1092805562), INT32_C( 1443901717), INT32_C( 1848749100), INT32_C( 1777333881), INT32_C( 1570116932), INT32_C(-1302383354), @@ -1559,7 +1559,7 @@ test_simde_mm512_maskz_inserti32x4(SIMDE_MUNIT_TEST_ARGS) { simde__m512i r1; simde__m512i r2; simde__m512i r3; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(21335), simde_mm512_set_epi32(INT32_C( 951544639), INT32_C(-1026363374), INT32_C(-1801776439), INT32_C( 145438126), INT32_C(-1306064352), INT32_C( -858736392), INT32_C( 923442479), INT32_C( 1092805562), @@ -1760,7 +1760,7 @@ test_simde_mm512_inserti64x4(SIMDE_MUNIT_TEST_ARGS) { simde__m256i b; simde__m512i r0; simde__m512i r1; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C( 4022993628330696330), INT64_C( -564047204985781920), INT64_C( 4934063986128071877), INT64_C( 8258886799903261224), INT64_C( 5245738308211416456), INT64_C( 8690736315259258337), @@ -1895,7 +1895,7 @@ test_simde_mm512_mask_inserti64x4(SIMDE_MUNIT_TEST_ARGS) { simde__m256i b; simde__m512i r0; simde__m512i r1; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C(-4408197122649025847), INT64_C( 624651997750430240), INT64_C(-3688244718601593553), INT64_C( 4693564151120802069), INT64_C( 7940316924786767481), INT64_C( 6743600876828439814), @@ -2069,7 +2069,7 @@ test_simde_mm512_maskz_inserti64x4(SIMDE_MUNIT_TEST_ARGS) { simde__m256i b; simde__m512i r0; simde__m512i r1; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 46), simde_mm512_set_epi64(INT64_C(-4408197122649025847), INT64_C( 624651997750430240), INT64_C(-3688244718601593553), INT64_C( 4693564151120802069), diff --git a/test/x86/avx512/loadu.c b/test/x86/avx512/loadu.c index 2b867cd10..260c3e58f 100644 --- a/test/x86/avx512/loadu.c +++ b/test/x86/avx512/loadu.c @@ -797,7 +797,7 @@ test_simde_mm512_loadu_si512(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu32(UINT32_C(2465927924), UINT32_C(3593197775), UINT32_C( 612910812), UINT32_C(3812769805), UINT32_C(4149829677), UINT32_C(3483799324), UINT32_C(1459962882), UINT32_C(4149819515), UINT32_C(2650201844), UINT32_C( 758753621), UINT32_C(1440172455), UINT32_C(1093653043), diff --git a/test/x86/avx512/mov.c b/test/x86/avx512/mov.c index ee828387b..79f12e8e3 100644 --- a/test/x86/avx512/mov.c +++ b/test/x86/avx512/mov.c @@ -433,7 +433,7 @@ test_simde_mm256_mask_mov_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__mmask32 k; simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C( -82), INT8_C( -32), INT8_C( -73), INT8_C( -78), INT8_C( -21), INT8_C( 76), INT8_C( 33), INT8_C( 90), INT8_C( -57), INT8_C( -12), INT8_C(-121), INT8_C( 101), @@ -651,7 +651,7 @@ test_simde_mm256_mask_mov_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi16(INT16_C(-23030), INT16_C( 6803), INT16_C(-21055), INT16_C( -910), INT16_C( -6009), INT16_C( 10471), INT16_C(-29834), INT16_C(-14111), INT16_C( -2981), INT16_C( 28733), INT16_C( 11699), INT16_C( 7781), @@ -773,7 +773,7 @@ test_simde_mm256_mask_mov_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C(-2051902106), INT32_C(-1489562810), INT32_C( -627115156), INT32_C( 913274595), INT32_C(-1198634499), INT32_C( 139959001), INT32_C(-1600412710), INT32_C( 934654383)), UINT8_C(164), @@ -847,7 +847,7 @@ test_simde_mm256_mask_mov_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C( -211287979567135941), INT64_C(-9075367401252635211), INT64_C( 960243121462097108), INT64_C( 2005878706758239899)), UINT8_C( 32), @@ -921,7 +921,7 @@ test_simde_mm256_mask_mov_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 774.53), SIMDE_FLOAT64_C( 377.61), SIMDE_FLOAT64_C( 717.45), SIMDE_FLOAT64_C( 713.04)), UINT8_C( 22), @@ -995,7 +995,7 @@ test_simde_mm256_mask_mov_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( -555.53), SIMDE_FLOAT32_C( 800.80), SIMDE_FLOAT32_C( 174.96), SIMDE_FLOAT32_C( 12.40), SIMDE_FLOAT32_C( -124.14), SIMDE_FLOAT32_C( 378.54), @@ -1117,7 +1117,7 @@ test_simde_mm512_mask_mov_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__mmask64 k; simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( -56), INT8_C( 10), INT8_C( 103), INT8_C( 84), INT8_C( 93), INT8_C( 24), INT8_C( -78), INT8_C( 35), INT8_C( 125), INT8_C( -63), INT8_C( 19), INT8_C( 4), @@ -1527,7 +1527,7 @@ test_simde_mm512_mask_mov_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__mmask32 k; simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi16(INT16_C( -1573), INT16_C( -6208), INT16_C(-22615), INT16_C( -3799), INT16_C( -8282), INT16_C(-15214), INT16_C(-19149), INT16_C(-11524), INT16_C(-31971), INT16_C( -228), INT16_C(-27669), INT16_C( 30774), @@ -1745,7 +1745,7 @@ test_simde_mm512_mask_mov_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C(-1748841636), INT32_C( 600342911), INT32_C( 1346502861), INT32_C(-1119296012), INT32_C( 542725165), INT32_C( 811581991), INT32_C(-1753809264), INT32_C(-2095888677), INT32_C( 21844621), INT32_C( -668859652), INT32_C( 304402382), INT32_C( 1173008100), @@ -1867,7 +1867,7 @@ test_simde_mm512_mask_mov_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C( 8729250599109288206), INT64_C( 925123000700261284), INT64_C( -996462675499144949), INT64_C(-5486361937319788764), INT64_C(-1619246833501834651), INT64_C(-1914665916415518359), @@ -1989,7 +1989,7 @@ test_simde_mm512_mask_mov_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -997.43), SIMDE_FLOAT64_C( -24.75), SIMDE_FLOAT64_C( 811.92), SIMDE_FLOAT64_C( 716.01), SIMDE_FLOAT64_C( -286.81), SIMDE_FLOAT64_C( 360.81), @@ -2111,7 +2111,7 @@ test_simde_mm512_mask_mov_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -278.44), SIMDE_FLOAT32_C( 958.04), SIMDE_FLOAT32_C( -686.18), SIMDE_FLOAT32_C( -120.52), SIMDE_FLOAT32_C( 759.91), SIMDE_FLOAT32_C( 470.87), SIMDE_FLOAT32_C( -723.57), SIMDE_FLOAT32_C( 170.04), SIMDE_FLOAT32_C( 559.73), SIMDE_FLOAT32_C( 984.13), SIMDE_FLOAT32_C( -84.72), SIMDE_FLOAT32_C( -543.95), @@ -2542,7 +2542,7 @@ test_simde_mm256_maskz_mov_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__mmask32 k; simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT32_C(1332074171), simde_mm256_set_epi8(INT8_C( 121), INT8_C( 75), INT8_C( 39), INT8_C(-100), INT8_C( 23), INT8_C( 80), INT8_C( 88), INT8_C( 14), @@ -2695,7 +2695,7 @@ test_simde_mm256_maskz_mov_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(41021), simde_mm256_set_epi16(INT16_C(-23030), INT16_C( 6803), INT16_C(-21055), INT16_C( -910), INT16_C( -6009), INT16_C( 10471), INT16_C(-29834), INT16_C(-14111), @@ -2784,7 +2784,7 @@ test_simde_mm256_maskz_mov_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C(205), simde_mm256_set_epi32(INT32_C( -433311806), INT32_C( 408583050), INT32_C( -306453652), INT32_C( -661693879), INT32_C( 1329919822), INT32_C( -49396337), INT32_C( -975523137), INT32_C( 228489302)), @@ -2841,7 +2841,7 @@ test_simde_mm256_maskz_mov_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m256i a; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C(109), simde_mm256_set_epi64x(INT64_C( 7572002691338055356), INT64_C(-6931202421771137023), INT64_C(-6376895216110561530), INT64_C( 101010879856088318)), @@ -2898,7 +2898,7 @@ test_simde_mm256_maskz_mov_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C(156), simde_mm256_set_pd(SIMDE_FLOAT64_C( -797.63), SIMDE_FLOAT64_C( 550.96), SIMDE_FLOAT64_C( 215.70), SIMDE_FLOAT64_C( -51.73)), @@ -2955,7 +2955,7 @@ test_simde_mm256_maskz_mov_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C(230), simde_mm256_set_ps(SIMDE_FLOAT32_C( -916.16), SIMDE_FLOAT32_C( -17.54), SIMDE_FLOAT32_C( 72.07), SIMDE_FLOAT32_C( 358.38), @@ -3044,7 +3044,7 @@ test_simde_mm512_maskz_mov_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__mmask64 k; simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT64_C( 5922492609958636327), simde_mm512_set_epi8(INT8_C( -97), INT8_C( -47), INT8_C( -93), INT8_C( -97), INT8_C( 9), INT8_C( -55), INT8_C(-113), INT8_C( 98), @@ -3325,7 +3325,7 @@ test_simde_mm512_maskz_mov_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__mmask32 k; simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT32_C(4000530422), simde_mm512_set_epi16(INT16_C( -5942), INT16_C( 25831), INT16_C(-28539), INT16_C( -1873), INT16_C(-13655), INT16_C( 26989), INT16_C( 16263), INT16_C( 13938), @@ -3478,7 +3478,7 @@ test_simde_mm512_maskz_mov_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(23562), simde_mm512_set_epi32(INT32_C( 413218138), INT32_C(-2056039012), INT32_C( 359898417), INT32_C( 503742711), INT32_C( -964140572), INT32_C( 1845540628), INT32_C( 1555270769), INT32_C( 276306907), @@ -3567,7 +3567,7 @@ test_simde_mm512_maskz_mov_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C(248), simde_mm512_set_epi64(INT64_C( 2197185227781835820), INT64_C( 15935016481556146), INT64_C(-7676897351944758395), INT64_C( -396609189869225788), @@ -3656,7 +3656,7 @@ test_simde_mm512_maskz_mov_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C(198), simde_mm512_set_pd(SIMDE_FLOAT64_C( -717.73), SIMDE_FLOAT64_C( -238.83), SIMDE_FLOAT64_C( -181.88), SIMDE_FLOAT64_C( -183.39), @@ -3745,7 +3745,7 @@ test_simde_mm512_maskz_mov_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(42363), simde_mm512_set_ps(SIMDE_FLOAT32_C( 27.87), SIMDE_FLOAT32_C( -816.11), SIMDE_FLOAT32_C( 100.70), SIMDE_FLOAT32_C( -687.21), SIMDE_FLOAT32_C( 641.77), SIMDE_FLOAT32_C( 431.46), SIMDE_FLOAT32_C( -432.41), SIMDE_FLOAT32_C( 128.97), diff --git a/test/x86/avx512/mov_mask.c b/test/x86/avx512/mov_mask.c index 6bc359109..05b68048c 100644 --- a/test/x86/avx512/mov_mask.c +++ b/test/x86/avx512/mov_mask.c @@ -434,7 +434,7 @@ test_simde_mm512_movepi8_mask(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512i a; simde__mmask64 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( 75), INT8_C( 84), INT8_C( -79), INT8_C( 113), INT8_C( -44), INT8_C( 119), INT8_C( -99), INT8_C( -4), INT8_C( 89), INT8_C(-108), INT8_C( -20), INT8_C( 38), @@ -586,7 +586,7 @@ test_simde_mm512_movepi16_mask(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512i a; simde__mmask32 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi16(INT16_C(-17047), INT16_C(-27489), INT16_C(-15227), INT16_C( 31130), INT16_C( 7900), INT16_C( 4229), INT16_C( 19494), INT16_C( -313), INT16_C( -7407), INT16_C( 6880), INT16_C( 31932), INT16_C(-13004), @@ -674,7 +674,7 @@ test_simde_mm512_movepi32_mask(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512i a; simde__mmask16 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( 949963630), INT32_C( 1064968775), INT32_C(-1905189849), INT32_C(-1560216302), INT32_C(-1667094448), INT32_C( 1432096084), INT32_C( 614973119), INT32_C( -938109633), INT32_C( -573293838), INT32_C(-1613148160), INT32_C( 914563081), INT32_C( -664378047), @@ -730,7 +730,7 @@ test_simde_mm512_movepi64_mask(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512i a; simde__mmask8 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C( 4315835916621638572), INT64_C(-6674257362849511307), INT64_C(-1762049467229420749), INT64_C(-8132359750587133268), INT64_C( 6148678802780014396), INT64_C( 4664933343968897426), diff --git a/test/x86/avx512/movm.c b/test/x86/avx512/movm.c index 53a1703d1..e3939ca88 100644 --- a/test/x86/avx512/movm.c +++ b/test/x86/avx512/movm.c @@ -91,7 +91,7 @@ test_simde_mm256_movm_epi8(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__mmask32 k; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT32_C(3131962838), simde_mm256_set_epi8(INT8_C( -1), INT8_C( 0), INT8_C( -1), INT8_C( -1), INT8_C( -1), INT8_C( 0), INT8_C( -1), INT8_C( 0), @@ -179,7 +179,7 @@ test_simde_mm512_movm_epi8(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__mmask64 k; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT64_C( 4739015484227475748), simde_mm512_set_epi8(INT8_C( 0), INT8_C( -1), INT8_C( 0), INT8_C( 0), INT8_C( 0), INT8_C( 0), INT8_C( 0), INT8_C( -1), @@ -371,7 +371,7 @@ test_simde_mm256_movm_epi16(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__mmask16 k; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C( 9176), simde_mm256_set_epi16(INT16_C( 0), INT16_C( 0), INT16_C( -1), INT16_C( 0), INT16_C( 0), INT16_C( 0), INT16_C( -1), INT16_C( -1), @@ -427,7 +427,7 @@ test_simde_mm512_movm_epi16(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__mmask32 k; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT32_C(2805036472), simde_mm512_set_epi16(INT16_C( -1), INT16_C( 0), INT16_C( -1), INT16_C( 0), INT16_C( 0), INT16_C( -1), INT16_C( -1), INT16_C( -1), @@ -547,7 +547,7 @@ test_simde_mm256_movm_epi32(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__mmask8 k; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C(216), simde_mm256_set_epi32(INT32_C( -1), INT32_C( -1), INT32_C( 0), INT32_C( -1), INT32_C( -1), INT32_C( 0), INT32_C( 0), INT32_C( 0)) }, @@ -587,7 +587,7 @@ test_simde_mm512_movm_epi32(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__mmask16 k; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(30136), simde_mm512_set_epi32(INT32_C( 0), INT32_C( -1), INT32_C( -1), INT32_C( -1), INT32_C( 0), INT32_C( -1), INT32_C( 0), INT32_C( -1), @@ -675,7 +675,7 @@ test_simde_mm256_movm_epi64(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__mmask8 k; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C(184), simde_mm256_set_epi64x(INT64_C( -1), INT64_C( 0), INT64_C( 0), INT64_C( 0)) }, @@ -715,7 +715,7 @@ test_simde_mm512_movm_epi64(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__mmask8 k; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C(184), simde_mm512_set_epi64(INT64_C( -1), INT64_C( 0), INT64_C( -1), INT64_C( -1), diff --git a/test/x86/avx512/mul.c b/test/x86/avx512/mul.c index e968473c9..8fe923bc4 100644 --- a/test/x86/avx512/mul.c +++ b/test/x86/avx512/mul.c @@ -107,7 +107,7 @@ test_simde_mm512_mask_mul_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C( 8259215308803572895), INT64_C( 5002417564910761422), INT64_C( 4825945910792190995), INT64_C(-3854692997504557014), INT64_C(-5029859126276555558), INT64_C(-6821356987634887986), @@ -261,7 +261,7 @@ test_simde_mm512_maskz_mul_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C(138), simde_mm512_set_epi32(INT32_C( 1098716707), INT32_C(-1080185167), INT32_C( 796032668), INT32_C( 1756455873), INT32_C(-1031023150), INT32_C( 313996055), INT32_C(-1552434635), INT32_C( 82580470), @@ -383,7 +383,7 @@ test_simde_mm512_maskz_mul_epu32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C(166), simde_x_mm512_set_epu32(UINT32_C(4120514587), UINT32_C(1586964835), UINT32_C(1689003642), UINT32_C(2702971618), UINT32_C(2798377561), UINT32_C( 356472812), UINT32_C(2899999566), UINT32_C(3229978818), @@ -504,7 +504,7 @@ test_simde_mm512_mul_epu32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu32(UINT32_C( 768255153), UINT32_C(3116504916), UINT32_C(2849349603), UINT32_C(3380602699), UINT32_C(3667150171), UINT32_C(2606748140), UINT32_C( 256440763), UINT32_C(4236376754), UINT32_C( 137611130), UINT32_C(3608004165), UINT32_C( 23379469), UINT32_C( 634104346), @@ -619,7 +619,7 @@ test_simde_mm512_mask_mul_epu32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu64(UINT64_C(11617731129322750966), UINT64_C( 2428231924375211538), UINT64_C(14175135673172244792), UINT64_C( 5480651963328574733), UINT64_C(12032129819668007160), UINT64_C( 4424822542185790875), @@ -772,7 +772,7 @@ test_simde_mm512_mul_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m512 a; simde__m512 b; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -775.40), SIMDE_FLOAT32_C( -210.92), SIMDE_FLOAT32_C( 987.42), SIMDE_FLOAT32_C( 542.45), SIMDE_FLOAT32_C( -745.60), SIMDE_FLOAT32_C( -50.38), SIMDE_FLOAT32_C( 163.82), SIMDE_FLOAT32_C( -164.62), SIMDE_FLOAT32_C( -736.65), SIMDE_FLOAT32_C( -764.30), SIMDE_FLOAT32_C( 675.25), SIMDE_FLOAT32_C( -182.15), @@ -887,7 +887,7 @@ test_simde_mm512_mask_mul_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m512 a; simde__m512 b; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( 229.27), SIMDE_FLOAT32_C( -114.91), SIMDE_FLOAT32_C( 520.43), SIMDE_FLOAT32_C( -755.19), SIMDE_FLOAT32_C( -68.64), SIMDE_FLOAT32_C( 632.30), SIMDE_FLOAT32_C( 98.14), SIMDE_FLOAT32_C( 455.87), SIMDE_FLOAT32_C( -873.22), SIMDE_FLOAT32_C( -223.86), SIMDE_FLOAT32_C( 181.32), SIMDE_FLOAT32_C( 364.92), @@ -1041,7 +1041,7 @@ test_simde_mm512_maskz_mul_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m512 a; simde__m512 b; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(47289), simde_mm512_set_ps(SIMDE_FLOAT32_C( -658.59), SIMDE_FLOAT32_C( -110.05), SIMDE_FLOAT32_C( -529.45), SIMDE_FLOAT32_C( 46.72), SIMDE_FLOAT32_C( -62.14), SIMDE_FLOAT32_C( 483.09), SIMDE_FLOAT32_C( 301.22), SIMDE_FLOAT32_C( -113.80), @@ -1162,7 +1162,7 @@ test_simde_mm512_mul_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512d a; simde__m512d b; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -736.65), SIMDE_FLOAT64_C( -764.30), SIMDE_FLOAT64_C( 675.25), SIMDE_FLOAT64_C( -182.15), SIMDE_FLOAT64_C( -748.44), SIMDE_FLOAT64_C( 82.10), @@ -1277,7 +1277,7 @@ test_simde_mm512_mask_mul_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512d a; simde__m512d b; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -821.30), SIMDE_FLOAT64_C( -768.64), SIMDE_FLOAT64_C( -18.18), SIMDE_FLOAT64_C( -679.16), SIMDE_FLOAT64_C( -992.98), SIMDE_FLOAT64_C( -764.30), @@ -1431,7 +1431,7 @@ test_simde_mm512_maskz_mul_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512d a; simde__m512d b; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 4), simde_mm512_set_pd(SIMDE_FLOAT64_C( 232.34), SIMDE_FLOAT64_C( 716.29), SIMDE_FLOAT64_C( 520.56), SIMDE_FLOAT64_C( -458.82), diff --git a/test/x86/avx512/or.c b/test/x86/avx512/or.c index 504c49843..738d06203 100644 --- a/test/x86/avx512/or.c +++ b/test/x86/avx512/or.c @@ -694,7 +694,7 @@ test_simde_mm512_or_si512(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( 1982508443), INT32_C( -368650443), INT32_C( -190462634), INT32_C( 1539812062), INT32_C( 1356046477), INT32_C( 862189546), INT32_C( 1762309251), INT32_C(-1019483096), INT32_C( 1873631110), INT32_C( -15642982), INT32_C( 1155728159), INT32_C( -93367878), diff --git a/test/x86/avx512/permutex2var.c b/test/x86/avx512/permutex2var.c index b9b393fcb..905121ecb 100644 --- a/test/x86/avx512/permutex2var.c +++ b/test/x86/avx512/permutex2var.c @@ -5175,7 +5175,7 @@ test_simde_mm512_permutex2var_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i idx; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( 1996766677), INT32_C( 914731069), INT32_C( 1945861252), INT32_C( 879354074), INT32_C( -643998219), INT32_C( -855842922), INT32_C( 1434025670), INT32_C( -672258087), INT32_C( 1290251647), INT32_C(-1094826982), INT32_C( 238338636), INT32_C( -252228416), @@ -5322,7 +5322,7 @@ test_simde_mm512_mask_permutex2var_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i idx; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C(-1026363374), INT32_C(-1801776439), INT32_C( 145438126), INT32_C(-1306064352), INT32_C( -858736392), INT32_C( 923442479), INT32_C( 1092805562), INT32_C( 1443901717), INT32_C( 1848749100), INT32_C( 1777333881), INT32_C( 1570116932), INT32_C(-1302383354), @@ -5477,7 +5477,7 @@ test_simde_mm512_mask2_permutex2var_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C(-1026363374), INT32_C(-1801776439), INT32_C( 145438126), INT32_C(-1306064352), INT32_C( -858736392), INT32_C( 923442479), INT32_C( 1092805562), INT32_C( 1443901717), INT32_C( 1848749100), INT32_C( 1777333881), INT32_C( 1570116932), INT32_C(-1302383354), @@ -5632,7 +5632,7 @@ test_simde_mm512_maskz_permutex2var_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i idx; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(21335), simde_mm512_set_epi32(INT32_C( 951544639), INT32_C(-1026363374), INT32_C(-1801776439), INT32_C( 145438126), INT32_C(-1306064352), INT32_C( -858736392), INT32_C( 923442479), INT32_C( 1092805562), @@ -5786,7 +5786,7 @@ test_simde_mm512_permutex2var_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i idx; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C( 4022993628330696330), INT64_C( -564047204985781920), INT64_C( 4934063986128071877), INT64_C( 8258886799903261224), INT64_C( 5245738308211416456), INT64_C( 8690736315259258337), @@ -5933,7 +5933,7 @@ test_simde_mm512_mask_permutex2var_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i idx; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C(-4408197122649025847), INT64_C( 624651997750430240), INT64_C(-3688244718601593553), INT64_C( 4693564151120802069), INT64_C( 7940316924786767481), INT64_C( 6743600876828439814), @@ -6088,7 +6088,7 @@ test_simde_mm512_mask2_permutex2var_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C(-4408197122649025847), INT64_C( 624651997750430240), INT64_C(-3688244718601593553), INT64_C( 4693564151120802069), INT64_C( 7940316924786767481), INT64_C( 6743600876828439814), @@ -6243,7 +6243,7 @@ test_simde_mm512_maskz_permutex2var_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i idx; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 87), simde_mm512_set_epi64(INT64_C( 4086853108457730066), INT64_C(-7738570880062900818), INT64_C(-5609503674875201288), INT64_C( 3966155248134972346), @@ -7602,7 +7602,7 @@ test_simde_mm512_permutex2var_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512i idx; simde__m512d b; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 799.30), SIMDE_FLOAT64_C( -576.01), SIMDE_FLOAT64_C( 439.15), SIMDE_FLOAT64_C( -28.15), SIMDE_FLOAT64_C( 481.25), SIMDE_FLOAT64_C( -784.26), @@ -7749,7 +7749,7 @@ test_simde_mm512_mask_permutex2var_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512i idx; simde__m512d b; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 160.98), SIMDE_FLOAT64_C( 391.82), SIMDE_FLOAT64_C( -569.99), SIMDE_FLOAT64_C( -327.63), SIMDE_FLOAT64_C( -172.36), SIMDE_FLOAT64_C( 393.53), @@ -7904,7 +7904,7 @@ test_simde_mm512_mask2_permutex2var_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512d b; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 824.77), SIMDE_FLOAT64_C( 172.30), SIMDE_FLOAT64_C( -660.39), SIMDE_FLOAT64_C( -605.88), SIMDE_FLOAT64_C( -689.22), SIMDE_FLOAT64_C( -25.12), @@ -8059,7 +8059,7 @@ test_simde_mm512_maskz_permutex2var_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512i idx; simde__m512d b; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 63), simde_mm512_set_pd(SIMDE_FLOAT64_C( 160.98), SIMDE_FLOAT64_C( 391.82), SIMDE_FLOAT64_C( -569.99), SIMDE_FLOAT64_C( -327.63), @@ -8213,7 +8213,7 @@ test_simde_mm512_permutex2var_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m512i idx; simde__m512 b; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -64.06), SIMDE_FLOAT32_C( 559.81), SIMDE_FLOAT32_C( -423.61), SIMDE_FLOAT32_C( 407.56), SIMDE_FLOAT32_C( -787.72), SIMDE_FLOAT32_C( -703.51), SIMDE_FLOAT32_C( -470.36), SIMDE_FLOAT32_C( 135.20), SIMDE_FLOAT32_C( 799.30), SIMDE_FLOAT32_C( -576.01), SIMDE_FLOAT32_C( 439.15), SIMDE_FLOAT32_C( -28.15), @@ -8364,7 +8364,7 @@ test_simde_mm512_mask_permutex2var_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m512i idx; simde__m512 b; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( 232.04), SIMDE_FLOAT32_C( 774.81), SIMDE_FLOAT32_C( -599.01), SIMDE_FLOAT32_C( 69.04), SIMDE_FLOAT32_C( -149.02), SIMDE_FLOAT32_C( 240.79), SIMDE_FLOAT32_C( -839.80), SIMDE_FLOAT32_C( -556.90), SIMDE_FLOAT32_C( 160.98), SIMDE_FLOAT32_C( 391.82), SIMDE_FLOAT32_C( -569.99), SIMDE_FLOAT32_C( -327.63), @@ -8519,7 +8519,7 @@ test_simde_mm512_mask2_permutex2var_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512 b; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( 877.96), SIMDE_FLOAT32_C( 184.43), SIMDE_FLOAT32_C( 375.34), SIMDE_FLOAT32_C( 389.76), SIMDE_FLOAT32_C( 437.16), SIMDE_FLOAT32_C( -638.93), SIMDE_FLOAT32_C( 773.45), SIMDE_FLOAT32_C( 109.31), SIMDE_FLOAT32_C( 824.77), SIMDE_FLOAT32_C( 172.30), SIMDE_FLOAT32_C( -660.39), SIMDE_FLOAT32_C( -605.88), @@ -8674,7 +8674,7 @@ test_simde_mm512_maskz_permutex2var_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m512i idx; simde__m512 b; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(45849), simde_mm512_set_ps(SIMDE_FLOAT32_C( 232.04), SIMDE_FLOAT32_C( 774.81), SIMDE_FLOAT32_C( -599.01), SIMDE_FLOAT32_C( 69.04), SIMDE_FLOAT32_C( -149.02), SIMDE_FLOAT32_C( 240.79), SIMDE_FLOAT32_C( -839.80), SIMDE_FLOAT32_C( -556.90), diff --git a/test/x86/avx512/permutexvar.c b/test/x86/avx512/permutexvar.c index fb7a17349..c52a095c6 100644 --- a/test/x86/avx512/permutexvar.c +++ b/test/x86/avx512/permutexvar.c @@ -2578,7 +2578,7 @@ test_simde_mm512_permutexvar_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i idx; simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( 1996766677), INT32_C( 914731069), INT32_C( 1945861252), INT32_C( 879354074), INT32_C( -643998219), INT32_C( -855842922), INT32_C( 1434025670), INT32_C( -672258087), INT32_C( 1290251647), INT32_C(-1094826982), INT32_C( 238338636), INT32_C( -252228416), @@ -2693,7 +2693,7 @@ test_simde_mm512_mask_permutexvar_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i idx; simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C(-1026363374), INT32_C(-1801776439), INT32_C( 145438126), INT32_C(-1306064352), INT32_C( -858736392), INT32_C( 923442479), INT32_C( 1092805562), INT32_C( 1443901717), INT32_C( 1848749100), INT32_C( 1777333881), INT32_C( 1570116932), INT32_C(-1302383354), @@ -2847,7 +2847,7 @@ test_simde_mm512_maskz_permutexvar_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i idx; simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(21335), simde_mm512_set_epi32(INT32_C( 951544639), INT32_C(-1026363374), INT32_C(-1801776439), INT32_C( 145438126), INT32_C(-1306064352), INT32_C( -858736392), INT32_C( 923442479), INT32_C( 1092805562), @@ -2968,7 +2968,7 @@ test_simde_mm512_permutexvar_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i idx; simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C(-2671339936797273634), INT64_C(-6569724575104779065), INT64_C( 6280671509806293744), INT64_C(-6564012982845614940), INT64_C(-8218226210083292891), INT64_C(-1970878168494992951), @@ -3083,7 +3083,7 @@ test_simde_mm512_mask_permutexvar_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i idx; simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C(-4408197122649025847), INT64_C( 624651997750430240), INT64_C(-3688244718601593553), INT64_C( 4693564151120802069), INT64_C( 7940316924786767481), INT64_C( 6743600876828439814), @@ -3237,7 +3237,7 @@ test_simde_mm512_maskz_permutexvar_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i idx; simde__m512i a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 87), simde_mm512_set_epi64(INT64_C( 4086853108457730066), INT64_C(-7738570880062900818), INT64_C(-5609503674875201288), INT64_C( 3966155248134972346), @@ -4123,7 +4123,7 @@ test_simde_mm512_permutexvar_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512i idx; simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C( 4022993628330696330), INT64_C( -564047204985781920), INT64_C( 4934063986128071877), INT64_C( 8258886799903261224), INT64_C( 5245738308211416456), INT64_C( 8690736315259258337), @@ -4238,7 +4238,7 @@ test_simde_mm512_mask_permutexvar_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512i idx; simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 903.50), SIMDE_FLOAT64_C( -43.35), SIMDE_FLOAT64_C( 309.91), SIMDE_FLOAT64_C( 846.15), SIMDE_FLOAT64_C( -514.56), SIMDE_FLOAT64_C( -860.98), @@ -4392,7 +4392,7 @@ test_simde_mm512_maskz_permutexvar_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512i idx; simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 87), simde_mm512_set_epi64(INT64_C( 4086853108457730066), INT64_C(-7738570880062900818), INT64_C(-5609503674875201288), INT64_C( 3966155248134972346), @@ -4513,7 +4513,7 @@ test_simde_mm512_permutexvar_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m512i idx; simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( 936676195), INT32_C( -430989686), INT32_C( -131327474), INT32_C( 910508384), INT32_C( 1148801293), INT32_C(-1204409147), INT32_C( 1922921929), INT32_C( 2087027240), INT32_C( 1221368626), INT32_C(-1114006136), INT32_C( 2023469730), INT32_C( 463308257), @@ -4628,7 +4628,7 @@ test_simde_mm512_mask_permutexvar_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m512i idx; simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -126.54), SIMDE_FLOAT32_C( 486.54), SIMDE_FLOAT32_C( 115.89), SIMDE_FLOAT32_C( 387.13), SIMDE_FLOAT32_C( -862.52), SIMDE_FLOAT32_C( -954.44), SIMDE_FLOAT32_C( -62.35), SIMDE_FLOAT32_C( -928.05), SIMDE_FLOAT32_C( 553.71), SIMDE_FLOAT32_C( 241.48), SIMDE_FLOAT32_C( -508.93), SIMDE_FLOAT32_C( 882.19), @@ -4782,7 +4782,7 @@ test_simde_mm512_maskz_permutexvar_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m512i idx; simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(21335), simde_mm512_set_epi32(INT32_C( 951544639), INT32_C(-1026363374), INT32_C(-1801776439), INT32_C( 145438126), INT32_C(-1306064352), INT32_C( -858736392), INT32_C( 923442479), INT32_C( 1092805562), diff --git a/test/x86/avx512/set1.c b/test/x86/avx512/set1.c index 3fbae0317..3b282f025 100644 --- a/test/x86/avx512/set1.c +++ b/test/x86/avx512/set1.c @@ -103,7 +103,7 @@ test_simde_mm512_set1_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde_float64 a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { SIMDE_FLOAT64_C( -426.34), simde_mm512_set_pd(SIMDE_FLOAT64_C( -426.34), SIMDE_FLOAT64_C( -426.34), SIMDE_FLOAT64_C( -426.34), SIMDE_FLOAT64_C( -426.34), @@ -159,7 +159,7 @@ test_simde_mm512_set1_epi8(SIMDE_MUNIT_TEST_ARGS) { const struct { int8_t a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { 15, simde_mm512_set_epi8(INT8_C( 15), INT8_C( 15), INT8_C( 15), INT8_C( 15), INT8_C( 15), INT8_C( 15), INT8_C( 15), INT8_C( 15), @@ -314,7 +314,7 @@ test_simde_mm512_mask_set1_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__mmask64 k; int8_t a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( 80), INT8_C( 13), INT8_C( -86), INT8_C( 103), INT8_C( 30), INT8_C( 88), INT8_C( -63), INT8_C( -16), INT8_C( -68), INT8_C( -20), INT8_C( 48), INT8_C( -36), @@ -603,7 +603,7 @@ test_simde_mm512_maskz_set1_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__mmask64 k; int8_t a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT64_C( 2901368310709582274), INT8_C( -37), simde_mm512_set_epi8(INT8_C( 0), INT8_C( 0), INT8_C( -37), INT8_C( 0), @@ -763,7 +763,7 @@ test_simde_mm512_set1_epi16(SIMDE_MUNIT_TEST_ARGS) { const struct { int16_t a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { -334, simde_mm512_set_epi16(INT16_C( -334), INT16_C( -334), INT16_C( -334), INT16_C( -334), INT16_C( -334), INT16_C( -334), INT16_C( -334), INT16_C( -334), @@ -853,7 +853,7 @@ test_simde_mm512_mask_set1_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__mmask32 k; int16_t a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi16(INT16_C( 874), INT16_C( 15357), INT16_C( 3602), INT16_C( 11090), INT16_C( 31475), INT16_C( 20808), INT16_C(-26328), INT16_C(-21794), INT16_C(-24829), INT16_C(-15530), INT16_C( -9785), INT16_C( 22806), @@ -1014,7 +1014,7 @@ test_simde_mm512_maskz_set1_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__mmask32 k; int16_t a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT32_C( 693683203), INT16_C(-16188), simde_mm512_set_epi16(INT16_C( 0), INT16_C( 0), INT16_C(-16188), INT16_C( 0), @@ -1110,7 +1110,7 @@ test_simde_mm512_set1_epi32(SIMDE_MUNIT_TEST_ARGS) { const struct { int32_t a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { 1727286739, simde_mm512_set_epi32(INT32_C( 1727286739), INT32_C( 1727286739), INT32_C( 1727286739), INT32_C( 1727286739), INT32_C( 1727286739), INT32_C( 1727286739), INT32_C( 1727286739), INT32_C( 1727286739), @@ -1168,7 +1168,7 @@ test_simde_mm512_mask_set1_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; int32_t a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C(-2133842294), INT32_C( 1453587049), INT32_C( 2146642803), INT32_C(-1231323727), INT32_C( 1853533908), INT32_C(-1907653908), INT32_C( 564694133), INT32_C(-1137944481), INT32_C( 355997036), INT32_C( 15257739), INT32_C( 1494729649), INT32_C( 1029796613), @@ -1265,7 +1265,7 @@ test_simde_mm512_maskz_set1_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; int32_t a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(55449), 1161879327, simde_mm512_set_epi32(INT32_C( 1161879327), INT32_C( 1161879327), INT32_C( 0), INT32_C( 1161879327), @@ -1329,7 +1329,7 @@ test_simde_mm512_set1_epi64(SIMDE_MUNIT_TEST_ARGS) { const struct { int64_t a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { -8789375007372599774, simde_mm512_set_epi64(INT64_C(-8789375007372599774), INT64_C(-8789375007372599774), INT64_C(-8789375007372599774), INT64_C(-8789375007372599774), @@ -1387,7 +1387,7 @@ test_simde_mm512_mask_set1_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; int64_t a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C( 1045216498523672669), INT64_C(-6036444540175881058), INT64_C(-5911148920502355606), INT64_C(-7577028982327639795), INT64_C(-2741592730704877834), INT64_C(-6453831303076951346), @@ -1484,7 +1484,7 @@ test_simde_mm512_maskz_set1_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; int64_t a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C(207), 9161374966470958313, simde_mm512_set_epi64(INT64_C( 9161374966470958313), INT64_C( 9161374966470958313), diff --git a/test/x86/avx512/set4.c b/test/x86/avx512/set4.c index 8a7205142..46a3ddfab 100644 --- a/test/x86/avx512/set4.c +++ b/test/x86/avx512/set4.c @@ -36,7 +36,7 @@ test_simde_mm512_set4_epi32(SIMDE_MUNIT_TEST_ARGS) { const struct { int32_t d; int32_t c; int32_t b; int32_t a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { INT32_C( 1704071444), INT32_C(-1428654423), INT32_C( 1780802031), @@ -116,7 +116,7 @@ test_simde_mm512_set4_epi64(SIMDE_MUNIT_TEST_ARGS) { const struct { int64_t d; int64_t c; int64_t b; int64_t a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { INT64_C(-2593705665723537468), INT64_C( 7248735595083828941), INT64_C(-1480325022577808917), @@ -196,7 +196,7 @@ test_simde_mm512_set4_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde_float32 d; simde_float32 c; simde_float32 b; simde_float32 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { SIMDE_FLOAT32_C( 549.42), SIMDE_FLOAT32_C( 390.74), SIMDE_FLOAT32_C( -762.45), @@ -276,7 +276,7 @@ test_simde_mm512_set4_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde_float64 d; simde_float64 c; simde_float64 b; simde_float64 a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { SIMDE_FLOAT64_C( -466.05), SIMDE_FLOAT64_C( -39.63), SIMDE_FLOAT64_C( 479.17), diff --git a/test/x86/avx512/setr.c b/test/x86/avx512/setr.c index 75b82f27b..d9d02a80b 100644 --- a/test/x86/avx512/setr.c +++ b/test/x86/avx512/setr.c @@ -37,7 +37,7 @@ test_simde_mm512_setr_epi32(SIMDE_MUNIT_TEST_ARGS) { int32_t e15; int32_t e14; int32_t e13; int32_t e12; int32_t e11; int32_t e10; int32_t e9; int32_t e8; int32_t e7; int32_t e6; int32_t e5; int32_t e4; int32_t e3; int32_t e2; int32_t e1; int32_t e0; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { INT32_C( -225639004), INT32_C( -150299519), INT32_C(-1534790107), @@ -214,7 +214,7 @@ test_simde_mm512_setr_epi64(SIMDE_MUNIT_TEST_ARGS) { const struct { int64_t e7; int64_t e6; int64_t e5; int64_t e4; int64_t e3; int64_t e2; int64_t e1; int64_t e0; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { INT64_C( 1888907496602700549), INT64_C(-4376226703742367928), INT64_C( 1319808302306308723), @@ -329,7 +329,7 @@ test_simde_mm512_setr_ps(SIMDE_MUNIT_TEST_ARGS) { simde_float32 e7; simde_float32 e6; simde_float32 e5; simde_float32 e4; simde_float32 e3; simde_float32 e2; simde_float32 e1; simde_float32 e0; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { SIMDE_FLOAT32_C( -693.34), SIMDE_FLOAT32_C( -391.55), SIMDE_FLOAT32_C( 340.77), @@ -508,7 +508,7 @@ test_simde_mm512_setr_pd(SIMDE_MUNIT_TEST_ARGS) { simde_float64 e7; simde_float64 e6; simde_float64 e5; simde_float64 e4; simde_float64 e3; simde_float64 e2; simde_float64 e1; simde_float64 e0; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { SIMDE_FLOAT64_C( -434.21), SIMDE_FLOAT64_C( -283.66), SIMDE_FLOAT64_C( 252.63), diff --git a/test/x86/avx512/setr4.c b/test/x86/avx512/setr4.c index a05a354ae..a274bdff8 100644 --- a/test/x86/avx512/setr4.c +++ b/test/x86/avx512/setr4.c @@ -36,7 +36,7 @@ test_simde_mm512_setr4_epi32(SIMDE_MUNIT_TEST_ARGS) { const struct { int32_t d; int32_t c; int32_t b; int32_t a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { INT32_C( 440568275), INT32_C(-1307171366), INT32_C( -667071334), @@ -116,7 +116,7 @@ test_simde_mm512_setr4_epi64(SIMDE_MUNIT_TEST_ARGS) { const struct { int64_t d; int64_t c; int64_t b; int64_t a; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { INT64_C( 6563849718269597141), INT64_C(-6183679436467555899), INT64_C( -626758305238464386), @@ -196,7 +196,7 @@ test_simde_mm512_setr4_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde_float32 d; simde_float32 c; simde_float32 b; simde_float32 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { SIMDE_FLOAT32_C( -92.68), SIMDE_FLOAT32_C( 845.12), SIMDE_FLOAT32_C( -953.73), @@ -276,7 +276,7 @@ test_simde_mm512_setr4_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde_float64 d; simde_float64 c; simde_float64 b; simde_float64 a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { SIMDE_FLOAT64_C( -159.85), SIMDE_FLOAT64_C( 360.42), SIMDE_FLOAT64_C( -560.02), diff --git a/test/x86/avx512/shuffle.c b/test/x86/avx512/shuffle.c index b028d4c61..c0af57b0d 100644 --- a/test/x86/avx512/shuffle.c +++ b/test/x86/avx512/shuffle.c @@ -37,7 +37,7 @@ test_simde_mm512_shuffle_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( 56), INT8_C( -94), INT8_C( -41), INT8_C( -59), INT8_C( 40), INT8_C( 78), INT8_C( 93), INT8_C( 107), INT8_C( -47), INT8_C( 66), INT8_C( -8), INT8_C( -52), @@ -440,7 +440,7 @@ test_simde_mm512_mask_shuffle_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( 92), INT8_C( 116), INT8_C( -78), INT8_C( -19), INT8_C( -73), INT8_C( 22), INT8_C( -66), INT8_C( -29), INT8_C( 55), INT8_C( 78), INT8_C( -45), INT8_C(-119), @@ -978,7 +978,7 @@ test_simde_mm512_maskz_shuffle_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT64_C(17286015531074160252), simde_mm512_set_epi8(INT8_C(-115), INT8_C( -27), INT8_C( 62), INT8_C( -85), INT8_C( 49), INT8_C(-115), INT8_C( 38), INT8_C( 4), diff --git a/test/x86/avx512/slli.c b/test/x86/avx512/slli.c index b7a4c9ec0..ced33bcce 100644 --- a/test/x86/avx512/slli.c +++ b/test/x86/avx512/slli.c @@ -259,7 +259,7 @@ test_simde_mm512_slli_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; unsigned int b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( -687706949), INT32_C( 1593775683), INT32_C( 332932989), INT32_C( 583872054), INT32_C( 1838832857), INT32_C( 847835558), INT32_C(-1396128258), INT32_C( -183977070), INT32_C( -902383138), INT32_C( -512492201), INT32_C(-1812249336), INT32_C( -562835271), @@ -348,7 +348,7 @@ test_simde_mm512_slli_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; unsigned int b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C(-2953678853593164221), INT64_C( 1429936300098399798), INT64_C( 7897726984473080230), INT64_C(-5996325205020460142), INT64_C(-3875706062389379753), INT64_C(-7783551626585583431), diff --git a/test/x86/avx512/srli.c b/test/x86/avx512/srli.c index 8ac10e847..a4bc0bfd5 100644 --- a/test/x86/avx512/srli.c +++ b/test/x86/avx512/srli.c @@ -118,7 +118,7 @@ test_simde_mm512_srli_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; unsigned int imm8; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C(-2020822652), INT32_C( -257395769), INT32_C( 499270536), INT32_C( 1400500940), INT32_C( 1373098033), INT32_C( 1102869287), INT32_C( 1033807112), INT32_C(-1561080563), INT32_C( 1506432231), INT32_C(-1063413574), INT32_C( 341686905), INT32_C( -287206476), @@ -207,7 +207,7 @@ test_simde_mm512_srli_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; unsigned int b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C( 7973262903512536694), INT64_C( -756652926976123625), INT64_C(-7907329678808178856), INT64_C(-4613066309848201378), INT64_C( 911796452309072772), INT64_C(-7947449538018331043), diff --git a/test/x86/avx512/sub.c b/test/x86/avx512/sub.c index 0ba97fc46..e2e0c9dca 100644 --- a/test/x86/avx512/sub.c +++ b/test/x86/avx512/sub.c @@ -38,7 +38,7 @@ test_simde_mm512_sub_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( 82), INT8_C( 83), INT8_C( 117), INT8_C( 65), INT8_C( -47), INT8_C(-122), INT8_C( 116), INT8_C( 14), INT8_C( 76), INT8_C( 1), INT8_C( -50), INT8_C( 4), @@ -441,7 +441,7 @@ test_simde_mm512_mask_sub_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( 121), INT8_C( -8), INT8_C(-121), INT8_C( -19), INT8_C( 19), INT8_C( -3), INT8_C( 10), INT8_C( -37), INT8_C( 96), INT8_C( 15), INT8_C( -45), INT8_C( -44), @@ -979,7 +979,7 @@ test_simde_mm512_maskz_sub_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT64_C( 3290745653), simde_mm512_set_epi8(INT8_C( 68), INT8_C( -18), INT8_C(-120), INT8_C( -91), INT8_C( 33), INT8_C( -44), INT8_C( 127), INT8_C(-128), @@ -1388,7 +1388,7 @@ test_simde_mm512_sub_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi16(INT16_C( 21075), INT16_C( 30017), INT16_C(-11898), INT16_C( 29710), INT16_C( 19457), INT16_C(-12796), INT16_C( 21427), INT16_C( 28826), INT16_C( 25482), INT16_C(-11843), INT16_C( 15582), INT16_C( 20114), @@ -1597,7 +1597,7 @@ test_simde_mm512_sub_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C(-2076524081), INT32_C( 1825078206), INT32_C(-1787857556), INT32_C(-1179707533), INT32_C( 233802890), INT32_C( 1015107327), INT32_C(-1130135421), INT32_C( 769270921), INT32_C( 970769619), INT32_C( -152032958), INT32_C(-1037455861), INT32_C( 1543352525), @@ -1710,7 +1710,7 @@ test_simde_mm512_sub_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C(-8918603015426376770), INT64_C(-7678789729811228813), INT64_C( 1004175767275392767), INT64_C(-4853894672476920695), INT64_C( 4169423769698314562), INT64_C(-4455838992495169331), @@ -1823,7 +1823,7 @@ test_simde_mm512_sub_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m512 a; simde__m512 b; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -659.63), SIMDE_FLOAT32_C( -759.67), SIMDE_FLOAT32_C( -847.92), SIMDE_FLOAT32_C( -61.45), SIMDE_FLOAT32_C( -337.36), SIMDE_FLOAT32_C( 139.68), SIMDE_FLOAT32_C( 658.69), SIMDE_FLOAT32_C( 86.55), SIMDE_FLOAT32_C( -150.13), SIMDE_FLOAT32_C( 450.66), SIMDE_FLOAT32_C( -527.30), SIMDE_FLOAT32_C( -641.78), @@ -1936,7 +1936,7 @@ test_simde_mm512_sub_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512d a; simde__m512d b; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -150.13), SIMDE_FLOAT64_C( 450.66), SIMDE_FLOAT64_C( -527.30), SIMDE_FLOAT64_C( -641.78), SIMDE_FLOAT64_C( 929.20), SIMDE_FLOAT64_C( -281.32), @@ -2051,7 +2051,7 @@ test_simde_mm512_mask_sub_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( -957186609), INT32_C(-1524765283), INT32_C( 1290068568), INT32_C( 1887468775), INT32_C( -904096999), INT32_C(-1189693212), INT32_C( 221355870), INT32_C(-1952779315), INT32_C( 1347985035), INT32_C(-2063939133), INT32_C(-1602582649), INT32_C(-2096850611), @@ -2206,7 +2206,7 @@ test_simde_mm512_mask_sub_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C( 8894478799917719473), INT64_C(-7614529333518044459), INT64_C( 8458392650500739529), INT64_C( 7085639313865748967), INT64_C(-7547504459018552290), INT64_C(-8310189466716392279), @@ -2361,7 +2361,7 @@ test_simde_mm512_mask_sub_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m512 a; simde__m512 b; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -417.79), SIMDE_FLOAT32_C( -912.83), SIMDE_FLOAT32_C( 111.29), SIMDE_FLOAT32_C( -470.87), SIMDE_FLOAT32_C( 685.45), SIMDE_FLOAT32_C( -92.85), SIMDE_FLOAT32_C( 704.55), SIMDE_FLOAT32_C( 450.79), SIMDE_FLOAT32_C( -761.01), SIMDE_FLOAT32_C( -759.35), SIMDE_FLOAT32_C( 646.77), SIMDE_FLOAT32_C( 616.33), @@ -2516,7 +2516,7 @@ test_simde_mm512_mask_sub_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512d a; simde__m512d b; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -621.09), SIMDE_FLOAT64_C( 350.18), SIMDE_FLOAT64_C( 873.40), SIMDE_FLOAT64_C( -136.67), SIMDE_FLOAT64_C( -484.90), SIMDE_FLOAT64_C( 672.37), @@ -2670,7 +2670,7 @@ test_simde_mm512_maskz_sub_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(42308), simde_mm512_set_epi32(INT32_C( 1724059665), INT32_C(-1181331137), INT32_C( -956878955), INT32_C( 1254662027), INT32_C( -334196329), INT32_C( -462422656), INT32_C( 391895544), INT32_C( 1081692585), @@ -2792,7 +2792,7 @@ test_simde_mm512_maskz_sub_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 68), simde_mm512_set_epi64(INT64_C(-5073778595823407211), INT64_C( 5388732377458839959), INT64_C(-1986090184057562632), INT64_C( 4645834279775613628), @@ -2914,7 +2914,7 @@ test_simde_mm512_maskz_sub_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m512 a; simde__m512 b; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(26074), simde_mm512_set_ps(SIMDE_FLOAT32_C( -524.33), SIMDE_FLOAT32_C( -241.59), SIMDE_FLOAT32_C( -105.89), SIMDE_FLOAT32_C( -289.61), SIMDE_FLOAT32_C( -891.58), SIMDE_FLOAT32_C( 378.73), SIMDE_FLOAT32_C( -71.99), SIMDE_FLOAT32_C( 449.90), @@ -3036,7 +3036,7 @@ test_simde_mm512_maskz_sub_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512d a; simde__m512d b; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 63), simde_mm512_set_pd(SIMDE_FLOAT64_C( -415.75), SIMDE_FLOAT64_C( 784.67), SIMDE_FLOAT64_C( -496.30), SIMDE_FLOAT64_C( 526.56), diff --git a/test/x86/avx512/subs.c b/test/x86/avx512/subs.c index 248b82980..993309c7f 100644 --- a/test/x86/avx512/subs.c +++ b/test/x86/avx512/subs.c @@ -37,7 +37,7 @@ test_simde_mm512_subs_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( 82), INT8_C( 83), INT8_C( 117), INT8_C( 65), INT8_C( -47), INT8_C(-122), INT8_C( 116), INT8_C( 14), INT8_C( 76), INT8_C( 1), INT8_C( -50), INT8_C( 4), @@ -440,7 +440,7 @@ test_simde_mm512_mask_subs_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( 52), INT8_C(-124), INT8_C( -17), INT8_C( -9), INT8_C( 31), INT8_C( 67), INT8_C( -76), INT8_C( -4), INT8_C( -52), INT8_C( 99), INT8_C( 106), INT8_C( -35), @@ -978,7 +978,7 @@ test_simde_mm512_maskz_subs_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT64_C( 2568138505), simde_mm512_set_epi8(INT8_C( 65), INT8_C( -91), INT8_C( -13), INT8_C( 114), INT8_C( 123), INT8_C( 107), INT8_C(-108), INT8_C( 15), @@ -1387,7 +1387,7 @@ test_simde_mm512_subs_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi16(INT16_C( 21075), INT16_C( 30017), INT16_C(-11898), INT16_C( 29710), INT16_C( 19457), INT16_C(-12796), INT16_C( 21427), INT16_C( 28826), INT16_C( 25482), INT16_C(-11843), INT16_C( 15582), INT16_C( 20114), @@ -1596,7 +1596,7 @@ test_simde_mm512_subs_epu8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu8(UINT8_C( 82), UINT8_C( 83), UINT8_C(117), UINT8_C( 65), UINT8_C(209), UINT8_C(134), UINT8_C(116), UINT8_C( 14), UINT8_C( 76), UINT8_C( 1), UINT8_C(206), UINT8_C( 4), @@ -1999,7 +1999,7 @@ test_simde_mm512_mask_subs_epu8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu8(UINT8_C(160), UINT8_C(209), UINT8_C( 53), UINT8_C(241), UINT8_C(169), UINT8_C( 74), UINT8_C(195), UINT8_C(156), UINT8_C(226), UINT8_C(114), UINT8_C(119), UINT8_C(203), @@ -2537,7 +2537,7 @@ test_simde_mm512_maskz_subs_epu8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT64_C( 1678504309), simde_x_mm512_set_epu8(UINT8_C(188), UINT8_C(227), UINT8_C(248), UINT8_C( 6), UINT8_C(158), UINT8_C(170), UINT8_C( 99), UINT8_C(202), @@ -2946,7 +2946,7 @@ test_simde_mm512_subs_epu16(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu16(UINT16_C( 21075), UINT16_C( 30017), UINT16_C( 53638), UINT16_C( 29710), UINT16_C( 19457), UINT16_C( 52740), UINT16_C( 21427), UINT16_C( 28826), UINT16_C( 25482), UINT16_C( 53693), UINT16_C( 15582), UINT16_C( 20114), diff --git a/test/x86/avx512/test.c b/test/x86/avx512/test.c index 0715f32d5..031bc8884 100644 --- a/test/x86/avx512/test.c +++ b/test/x86/avx512/test.c @@ -162,7 +162,7 @@ test_simde_mm512_mask_test_epi32_mask(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__mmask16 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT16_C(13733), simde_mm512_set_epi32(INT32_C(-1058044212), INT32_C( 1745554146), INT32_C( -938028173), INT32_C( 1123843978), INT32_C( 0), INT32_C( 369104615), INT32_C( 288860030), INT32_C( 0), @@ -260,7 +260,7 @@ test_simde_mm512_mask_test_epi64_mask(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__mmask8 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT8_C( 51), simde_mm512_set_epi64(INT64_C(-1021777151925940720), INT64_C(-8606874489654438743), INT64_C( 2982642907250026668), INT64_C( 1121557266302837638), diff --git a/test/x86/avx512/xor.c b/test/x86/avx512/xor.c index 083dc3de3..ee754ba99 100644 --- a/test/x86/avx512/xor.c +++ b/test/x86/avx512/xor.c @@ -646,7 +646,7 @@ test_simde_mm512_xor_si512(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu64(UINT64_C(0xedb78aa51009d043), UINT64_C(0xf8d6e1466c80412e), UINT64_C(0x8d2f88ccf8d072d2), UINT64_C(0xd42ce380801d56eb), UINT64_C(0x4f7a9f9f877cf207), UINT64_C(0x9ebf29784a068fec), diff --git a/test/x86/fma.c b/test/x86/fma.c index 87bedf19a..b6c05319c 100644 --- a/test/x86/fma.c +++ b/test/x86/fma.c @@ -82,7 +82,7 @@ test_simde_mm256_fmadd_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d b; simde__m256d c; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 463.71), SIMDE_FLOAT64_C( -551.83), SIMDE_FLOAT64_C( 568.05), SIMDE_FLOAT64_C( -826.17)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 440.29), SIMDE_FLOAT64_C( 762.39), @@ -214,7 +214,7 @@ test_simde_mm256_fmadd_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 b; simde__m256 c; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 39.90), SIMDE_FLOAT32_C( 46.80), SIMDE_FLOAT32_C( -90.30), SIMDE_FLOAT32_C( -57.20), SIMDE_FLOAT32_C( 71.50), SIMDE_FLOAT32_C( 75.00), @@ -510,7 +510,7 @@ test_simde_mm256_fmaddsub_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d b; simde__m256d c; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -52.10), SIMDE_FLOAT64_C( -92.00), SIMDE_FLOAT64_C( -82.90), SIMDE_FLOAT64_C( -49.00)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -49.30), SIMDE_FLOAT64_C( -97.40), @@ -642,7 +642,7 @@ test_simde_mm256_fmaddsub_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 b; simde__m256 c; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( -61.10), SIMDE_FLOAT32_C( -95.60), SIMDE_FLOAT32_C( 56.00), SIMDE_FLOAT32_C( 46.30), SIMDE_FLOAT32_C( -62.80), SIMDE_FLOAT32_C( 38.90), @@ -838,7 +838,7 @@ test_simde_mm256_fmsub_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d b; simde__m256d c; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 34.80), SIMDE_FLOAT64_C( 57.60), SIMDE_FLOAT64_C( 21.20), SIMDE_FLOAT64_C( 58.70)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -15.50), SIMDE_FLOAT64_C( -85.90), @@ -970,7 +970,7 @@ test_simde_mm256_fmsub_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 b; simde__m256 c; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 71.60), SIMDE_FLOAT32_C( 70.70), SIMDE_FLOAT32_C( 40.60), SIMDE_FLOAT32_C( -9.30), SIMDE_FLOAT32_C( -79.10), SIMDE_FLOAT32_C( 52.30), @@ -1266,7 +1266,7 @@ test_simde_mm256_fmsubadd_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d b; simde__m256d c; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -49.40), SIMDE_FLOAT64_C( -57.60), SIMDE_FLOAT64_C( -73.20), SIMDE_FLOAT64_C( -70.10)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -0.10), SIMDE_FLOAT64_C( 46.20), @@ -1398,7 +1398,7 @@ test_simde_mm256_fmsubadd_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 b; simde__m256 c; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 80.60), SIMDE_FLOAT32_C( -80.20), SIMDE_FLOAT32_C( 25.10), SIMDE_FLOAT32_C( 54.40), SIMDE_FLOAT32_C( -94.50), SIMDE_FLOAT32_C( -99.70), @@ -1594,7 +1594,7 @@ test_simde_mm256_fnmadd_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d b; simde__m256d c; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 17.60), SIMDE_FLOAT64_C( -99.20), SIMDE_FLOAT64_C( 64.80), SIMDE_FLOAT64_C( -66.40)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -84.50), SIMDE_FLOAT64_C( 62.70), @@ -1726,7 +1726,7 @@ test_simde_mm256_fnmadd_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 b; simde__m256 c; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( -74.50), SIMDE_FLOAT32_C( 76.00), SIMDE_FLOAT32_C( -65.60), SIMDE_FLOAT32_C( -57.80), SIMDE_FLOAT32_C( 48.90), SIMDE_FLOAT32_C( 17.90), @@ -2022,7 +2022,7 @@ test_simde_mm256_fnmsub_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d b; simde__m256d c; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -97.30), SIMDE_FLOAT64_C( 40.60), SIMDE_FLOAT64_C( -78.70), SIMDE_FLOAT64_C( 0.60)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 43.40), SIMDE_FLOAT64_C( -67.40), @@ -2154,7 +2154,7 @@ test_simde_mm256_fnmsub_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 b; simde__m256 c; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( -91.80), SIMDE_FLOAT32_C( -53.10), SIMDE_FLOAT32_C( -79.10), SIMDE_FLOAT32_C( 50.50), SIMDE_FLOAT32_C( -81.20), SIMDE_FLOAT32_C( -11.90), diff --git a/test/x86/gfni.c b/test/x86/gfni.c index c86b0c915..2fbe060e8 100644 --- a/test/x86/gfni.c +++ b/test/x86/gfni.c @@ -144,7 +144,7 @@ test_simde_mm256_gf2p8affine_epi64_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i x; simde__m256i A; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C(-125), INT8_C( 82), INT8_C( -93), INT8_C(-115), INT8_C( 48), INT8_C( 63), INT8_C( -3), INT8_C( 71), INT8_C( 31), INT8_C( -71), INT8_C(-118), INT8_C( 42), @@ -353,7 +353,7 @@ test_simde_mm512_gf2p8affine_epi64_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i x; simde__m512i A; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( 91), INT8_C(-104), INT8_C( 75), INT8_C( 27), INT8_C( 22), INT8_C( 10), INT8_C( 2), INT8_C( -59), INT8_C( -6), INT8_C( -24), INT8_C( 10), INT8_C( 64), @@ -911,7 +911,7 @@ test_simde_mm256_mask_gf2p8affine_epi64_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i x; simde__m256i A; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C( -91), INT8_C( 125), INT8_C( -59), INT8_C( -28), INT8_C(-110), INT8_C( 94), INT8_C( 67), INT8_C( 64), INT8_C( -85), INT8_C( 127), INT8_C( -76), INT8_C(-117), @@ -1194,7 +1194,7 @@ test_simde_mm512_mask_gf2p8affine_epi64_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i x; simde__m512i A; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( -38), INT8_C( -31), INT8_C( -26), INT8_C(-115), INT8_C(-118), INT8_C( 4), INT8_C( -21), INT8_C( 76), INT8_C( -18), INT8_C( 56), INT8_C( -33), INT8_C( 5), @@ -1854,7 +1854,7 @@ test_simde_mm256_maskz_gf2p8affine_epi64_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i x; simde__m256i A; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT32_C(2667081570), simde_mm256_set_epi8(INT8_C(-117), INT8_C( -3), INT8_C( 125), INT8_C(-126), INT8_C( 35), INT8_C( 127), INT8_C( 14), INT8_C( 124), @@ -2072,7 +2072,7 @@ test_simde_mm512_maskz_gf2p8affine_epi64_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i x; simde__m512i A; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT64_C( 2216089611417448290), simde_mm512_set_epi8(INT8_C( 54), INT8_C( 27), INT8_C( -19), INT8_C( 2), INT8_C( -62), INT8_C( -13), INT8_C( -21), INT8_C( 121), @@ -2594,7 +2594,7 @@ test_simde_mm256_gf2p8affineinv_epi64_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i x; simde__m256i A; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C( -23), INT8_C( 64), INT8_C( 17), INT8_C(-118), INT8_C(-108), INT8_C(-111), INT8_C( 0), INT8_C( 45), INT8_C( 94), INT8_C( 64), INT8_C( 99), INT8_C( -32), @@ -2803,7 +2803,7 @@ test_simde_mm512_gf2p8affineinv_epi64_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i x; simde__m512i A; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( -33), INT8_C( 19), INT8_C( -14), INT8_C( 38), INT8_C( -80), INT8_C( -72), INT8_C( 4), INT8_C( -22), INT8_C( 57), INT8_C( -46), INT8_C( 98), INT8_C( -35), @@ -3361,7 +3361,7 @@ test_simde_mm256_mask_gf2p8affineinv_epi64_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i x; simde__m256i A; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C( 102), INT8_C( -48), INT8_C( 124), INT8_C( 70), INT8_C( 47), INT8_C( 38), INT8_C( 113), INT8_C( -68), INT8_C( -88), INT8_C( 75), INT8_C( 45), INT8_C( 101), @@ -3644,7 +3644,7 @@ test_simde_mm512_mask_gf2p8affineinv_epi64_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i x; simde__m512i A; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( -60), INT8_C(-108), INT8_C( 94), INT8_C( -85), INT8_C( 51), INT8_C( 20), INT8_C( 52), INT8_C(-114), INT8_C( -6), INT8_C( 43), INT8_C( 55), INT8_C( 12), @@ -4304,7 +4304,7 @@ test_simde_mm256_maskz_gf2p8affineinv_epi64_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i x; simde__m256i A; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT32_C(1396440709), simde_mm256_set_epi8(INT8_C( -42), INT8_C( 62), INT8_C( 88), INT8_C( 7), INT8_C( 61), INT8_C( 116), INT8_C( -89), INT8_C( 122), @@ -4522,7 +4522,7 @@ test_simde_mm512_maskz_gf2p8affineinv_epi64_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i x; simde__m512i A; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT64_C( 2674908657002217093), simde_mm512_set_epi8(INT8_C( 78), INT8_C( -70), INT8_C( 8), INT8_C( -28), INT8_C( -17), INT8_C( 126), INT8_C(-111), INT8_C(-124), @@ -5044,7 +5044,7 @@ test_simde_mm256_gf2p8mul_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C( -64), INT8_C( 5), INT8_C( -52), INT8_C( 61), INT8_C( 44), INT8_C( 127), INT8_C( 41), INT8_C( 104), INT8_C(-104), INT8_C( 0), INT8_C( 31), INT8_C(-117), @@ -5253,7 +5253,7 @@ test_simde_mm512_gf2p8mul_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( -4), INT8_C( -99), INT8_C( -5), INT8_C( 60), INT8_C( -45), INT8_C( 78), INT8_C( -33), INT8_C( 92), INT8_C( 53), INT8_C( -32), INT8_C( 109), INT8_C( -22), @@ -5811,7 +5811,7 @@ test_simde_mm256_mask_gf2p8mul_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C( -91), INT8_C( -2), INT8_C( -76), INT8_C( 64), INT8_C( -37), INT8_C( 76), INT8_C( -74), INT8_C( 84), INT8_C( 46), INT8_C(-109), INT8_C( -48), INT8_C( -25), @@ -6094,7 +6094,7 @@ test_simde_mm512_mask_gf2p8mul_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( -60), INT8_C( 108), INT8_C( -83), INT8_C( -82), INT8_C( 83), INT8_C( 115), INT8_C( 91), INT8_C( 16), INT8_C( -37), INT8_C( -12), INT8_C( -15), INT8_C( -3), @@ -6754,7 +6754,7 @@ test_simde_mm256_maskz_gf2p8mul_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT32_C(2075432365), simde_mm256_set_epi8(INT8_C( 86), INT8_C( 126), INT8_C( -66), INT8_C( -91), INT8_C( -5), INT8_C(-106), INT8_C( -15), INT8_C( 89), @@ -6972,7 +6972,7 @@ test_simde_mm512_maskz_gf2p8mul_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { UINT64_C( 563128178629459346), simde_mm512_set_epi8(INT8_C( -18), INT8_C( 102), INT8_C( 52), INT8_C( -28), INT8_C( -18), INT8_C( 37), INT8_C(-101), INT8_C( -22), diff --git a/test/x86/svml.c b/test/x86/svml.c index 5607bb538..9c510f08c 100644 --- a/test/x86/svml.c +++ b/test/x86/svml.c @@ -95,7 +95,7 @@ test_simde_mm256_acos_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 0.50), SIMDE_FLOAT32_C( 0.67), SIMDE_FLOAT32_C( -0.30), SIMDE_FLOAT32_C( 0.03), SIMDE_FLOAT32_C( -0.19), SIMDE_FLOAT32_C( 0.04), @@ -175,7 +175,7 @@ test_simde_mm256_acos_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -0.19), SIMDE_FLOAT64_C( 0.04), SIMDE_FLOAT64_C( -0.75), SIMDE_FLOAT64_C( 0.35)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 1.76), SIMDE_FLOAT64_C( 1.53), @@ -223,7 +223,7 @@ test_simde_mm512_acos_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -0.68), SIMDE_FLOAT32_C( -0.69), SIMDE_FLOAT32_C( 0.08), SIMDE_FLOAT32_C( 0.57), SIMDE_FLOAT32_C( 0.83), SIMDE_FLOAT32_C( 0.42), SIMDE_FLOAT32_C( -0.27), SIMDE_FLOAT32_C( 0.47), SIMDE_FLOAT32_C( 0.50), SIMDE_FLOAT32_C( 0.67), SIMDE_FLOAT32_C( -0.30), SIMDE_FLOAT32_C( 0.03), @@ -305,7 +305,7 @@ test_simde_mm512_mask_acos_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -0.45), SIMDE_FLOAT32_C( 0.69), SIMDE_FLOAT32_C( -0.21), SIMDE_FLOAT32_C( -0.66), SIMDE_FLOAT32_C( 0.03), SIMDE_FLOAT32_C( -0.92), SIMDE_FLOAT32_C( -0.86), SIMDE_FLOAT32_C( 0.70), SIMDE_FLOAT32_C( -0.69), SIMDE_FLOAT32_C( 0.57), SIMDE_FLOAT32_C( 0.42), SIMDE_FLOAT32_C( 0.47), @@ -425,7 +425,7 @@ test_simde_mm512_acos_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 0.50), SIMDE_FLOAT64_C( 0.67), SIMDE_FLOAT64_C( -0.30), SIMDE_FLOAT64_C( 0.03), SIMDE_FLOAT64_C( -0.19), SIMDE_FLOAT64_C( 0.04), @@ -507,7 +507,7 @@ test_simde_mm512_mask_acos_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -0.69), SIMDE_FLOAT64_C( 0.57), SIMDE_FLOAT64_C( 0.42), SIMDE_FLOAT64_C( 0.47), SIMDE_FLOAT64_C( 0.67), SIMDE_FLOAT64_C( 0.03), @@ -691,7 +691,7 @@ test_simde_mm256_acosh_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 5.94), SIMDE_FLOAT32_C( 6.51), SIMDE_FLOAT32_C( 3.32), SIMDE_FLOAT32_C( 4.41), SIMDE_FLOAT32_C( 3.69), SIMDE_FLOAT32_C( 4.43), @@ -771,7 +771,7 @@ test_simde_mm256_acosh_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 3.69), SIMDE_FLOAT64_C( 4.43), SIMDE_FLOAT64_C( 1.81), SIMDE_FLOAT64_C( 5.44)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 1.98), SIMDE_FLOAT64_C( 2.17), @@ -819,7 +819,7 @@ test_simde_mm512_acosh_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( 2.06), SIMDE_FLOAT32_C( 2.04), SIMDE_FLOAT32_C( 4.58), SIMDE_FLOAT32_C( 6.19), SIMDE_FLOAT32_C( 7.02), SIMDE_FLOAT32_C( 5.69), SIMDE_FLOAT32_C( 3.41), SIMDE_FLOAT32_C( 5.84), SIMDE_FLOAT32_C( 5.94), SIMDE_FLOAT32_C( 6.51), SIMDE_FLOAT32_C( 3.32), SIMDE_FLOAT32_C( 4.41), @@ -901,7 +901,7 @@ test_simde_mm512_mask_acosh_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( 2.81), SIMDE_FLOAT32_C( 6.57), SIMDE_FLOAT32_C( 3.60), SIMDE_FLOAT32_C( 2.12), SIMDE_FLOAT32_C( 4.39), SIMDE_FLOAT32_C( 1.25), SIMDE_FLOAT32_C( 1.46), SIMDE_FLOAT32_C( 6.60), SIMDE_FLOAT32_C( 2.04), SIMDE_FLOAT32_C( 6.19), SIMDE_FLOAT32_C( 5.69), SIMDE_FLOAT32_C( 5.84), @@ -1021,7 +1021,7 @@ test_simde_mm512_acosh_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 5.94), SIMDE_FLOAT64_C( 6.51), SIMDE_FLOAT64_C( 3.32), SIMDE_FLOAT64_C( 4.41), SIMDE_FLOAT64_C( 3.69), SIMDE_FLOAT64_C( 4.43), @@ -1103,7 +1103,7 @@ test_simde_mm512_mask_acosh_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 2.04), SIMDE_FLOAT64_C( 6.19), SIMDE_FLOAT64_C( 5.69), SIMDE_FLOAT64_C( 5.84), SIMDE_FLOAT64_C( 6.51), SIMDE_FLOAT64_C( 4.41), @@ -1287,7 +1287,7 @@ test_simde_mm256_asin_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 0.50), SIMDE_FLOAT32_C( 0.67), SIMDE_FLOAT32_C( -0.30), SIMDE_FLOAT32_C( 0.03), SIMDE_FLOAT32_C( -0.19), SIMDE_FLOAT32_C( 0.04), @@ -1367,7 +1367,7 @@ test_simde_mm256_asin_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -0.19), SIMDE_FLOAT64_C( 0.04), SIMDE_FLOAT64_C( -0.75), SIMDE_FLOAT64_C( 0.35)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -0.19), SIMDE_FLOAT64_C( 0.04), @@ -1415,7 +1415,7 @@ test_simde_mm512_asin_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -0.68), SIMDE_FLOAT32_C( -0.69), SIMDE_FLOAT32_C( 0.08), SIMDE_FLOAT32_C( 0.57), SIMDE_FLOAT32_C( 0.83), SIMDE_FLOAT32_C( 0.42), SIMDE_FLOAT32_C( -0.27), SIMDE_FLOAT32_C( 0.47), SIMDE_FLOAT32_C( 0.50), SIMDE_FLOAT32_C( 0.67), SIMDE_FLOAT32_C( -0.30), SIMDE_FLOAT32_C( 0.03), @@ -1497,7 +1497,7 @@ test_simde_mm512_mask_asin_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -0.45), SIMDE_FLOAT32_C( 0.69), SIMDE_FLOAT32_C( -0.21), SIMDE_FLOAT32_C( -0.66), SIMDE_FLOAT32_C( 0.03), SIMDE_FLOAT32_C( -0.92), SIMDE_FLOAT32_C( -0.86), SIMDE_FLOAT32_C( 0.70), SIMDE_FLOAT32_C( -0.69), SIMDE_FLOAT32_C( 0.57), SIMDE_FLOAT32_C( 0.42), SIMDE_FLOAT32_C( 0.47), @@ -1617,7 +1617,7 @@ test_simde_mm512_asin_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 0.50), SIMDE_FLOAT64_C( 0.67), SIMDE_FLOAT64_C( -0.30), SIMDE_FLOAT64_C( 0.03), SIMDE_FLOAT64_C( -0.19), SIMDE_FLOAT64_C( 0.04), @@ -1699,7 +1699,7 @@ test_simde_mm512_mask_asin_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -0.69), SIMDE_FLOAT64_C( 0.57), SIMDE_FLOAT64_C( 0.42), SIMDE_FLOAT64_C( 0.47), SIMDE_FLOAT64_C( 0.67), SIMDE_FLOAT64_C( 0.03), @@ -1883,7 +1883,7 @@ test_simde_mm256_asinh_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 497.31), SIMDE_FLOAT32_C( 670.24), SIMDE_FLOAT32_C( -297.45), SIMDE_FLOAT32_C( 34.06), SIMDE_FLOAT32_C( -186.21), SIMDE_FLOAT32_C( 39.01), @@ -1963,7 +1963,7 @@ test_simde_mm256_asinh_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -186.21), SIMDE_FLOAT64_C( 39.01), SIMDE_FLOAT64_C( -754.38), SIMDE_FLOAT64_C( 346.63)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -5.92), SIMDE_FLOAT64_C( 4.36), @@ -2011,7 +2011,7 @@ test_simde_mm512_asinh_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -678.17), SIMDE_FLOAT32_C( -686.13), SIMDE_FLOAT32_C( 84.77), SIMDE_FLOAT32_C( 571.46), SIMDE_FLOAT32_C( 825.53), SIMDE_FLOAT32_C( 422.21), SIMDE_FLOAT32_C( -269.45), SIMDE_FLOAT32_C( 467.76), SIMDE_FLOAT32_C( 497.31), SIMDE_FLOAT32_C( 670.24), SIMDE_FLOAT32_C( -297.45), SIMDE_FLOAT32_C( 34.06), @@ -2093,7 +2093,7 @@ test_simde_mm512_mask_asinh_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -450.67), SIMDE_FLOAT32_C( 687.09), SIMDE_FLOAT32_C( -212.54), SIMDE_FLOAT32_C( -660.80), SIMDE_FLOAT32_C( 28.47), SIMDE_FLOAT32_C( -923.64), SIMDE_FLOAT32_C( -860.95), SIMDE_FLOAT32_C( 696.87), SIMDE_FLOAT32_C( -686.13), SIMDE_FLOAT32_C( 571.46), SIMDE_FLOAT32_C( 422.21), SIMDE_FLOAT32_C( 467.76), @@ -2213,7 +2213,7 @@ test_simde_mm512_asinh_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 497.31), SIMDE_FLOAT64_C( 670.24), SIMDE_FLOAT64_C( -297.45), SIMDE_FLOAT64_C( 34.06), SIMDE_FLOAT64_C( -186.21), SIMDE_FLOAT64_C( 39.01), @@ -2295,7 +2295,7 @@ test_simde_mm512_mask_asinh_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -686.13), SIMDE_FLOAT64_C( 571.46), SIMDE_FLOAT64_C( 422.21), SIMDE_FLOAT64_C( 467.76), SIMDE_FLOAT64_C( 670.24), SIMDE_FLOAT64_C( 34.06), @@ -2479,7 +2479,7 @@ test_simde_mm256_atan_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 497.31), SIMDE_FLOAT32_C( 670.24), SIMDE_FLOAT32_C( -297.45), SIMDE_FLOAT32_C( 34.06), SIMDE_FLOAT32_C( -186.21), SIMDE_FLOAT32_C( 39.01), @@ -2559,7 +2559,7 @@ test_simde_mm256_atan_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -186.21), SIMDE_FLOAT64_C( 39.01), SIMDE_FLOAT64_C( -754.38), SIMDE_FLOAT64_C( 346.63)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -1.57), SIMDE_FLOAT64_C( 1.55), @@ -2607,7 +2607,7 @@ test_simde_mm512_atan_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -678.17), SIMDE_FLOAT32_C( -686.13), SIMDE_FLOAT32_C( 84.77), SIMDE_FLOAT32_C( 571.46), SIMDE_FLOAT32_C( 825.53), SIMDE_FLOAT32_C( 422.21), SIMDE_FLOAT32_C( -269.45), SIMDE_FLOAT32_C( 467.76), SIMDE_FLOAT32_C( 497.31), SIMDE_FLOAT32_C( 670.24), SIMDE_FLOAT32_C( -297.45), SIMDE_FLOAT32_C( 34.06), @@ -2689,7 +2689,7 @@ test_simde_mm512_mask_atan_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -450.67), SIMDE_FLOAT32_C( 687.09), SIMDE_FLOAT32_C( -212.54), SIMDE_FLOAT32_C( -660.80), SIMDE_FLOAT32_C( 28.47), SIMDE_FLOAT32_C( -923.64), SIMDE_FLOAT32_C( -860.95), SIMDE_FLOAT32_C( 696.87), SIMDE_FLOAT32_C( -686.13), SIMDE_FLOAT32_C( 571.46), SIMDE_FLOAT32_C( 422.21), SIMDE_FLOAT32_C( 467.76), @@ -2809,7 +2809,7 @@ test_simde_mm512_atan_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 497.31), SIMDE_FLOAT64_C( 670.24), SIMDE_FLOAT64_C( -297.45), SIMDE_FLOAT64_C( 34.06), SIMDE_FLOAT64_C( -186.21), SIMDE_FLOAT64_C( 39.01), @@ -2891,7 +2891,7 @@ test_simde_mm512_mask_atan_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -686.13), SIMDE_FLOAT64_C( 571.46), SIMDE_FLOAT64_C( 422.21), SIMDE_FLOAT64_C( 467.76), SIMDE_FLOAT64_C( 670.24), SIMDE_FLOAT64_C( 34.06), @@ -3097,7 +3097,7 @@ test_simde_mm256_atan2_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m256 a; simde__m256 b; simde__m256 r; - } test_vec[9] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[9] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( -686.13), SIMDE_FLOAT32_C( 571.46), SIMDE_FLOAT32_C( 422.21), SIMDE_FLOAT32_C( 467.76), SIMDE_FLOAT32_C( 670.24), SIMDE_FLOAT32_C( 34.06), @@ -3223,7 +3223,7 @@ test_simde_mm256_atan2_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m256d a; simde__m256d b; simde__m256d r; - } test_vec[9] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[9] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 670.24), SIMDE_FLOAT64_C( 34.06), SIMDE_FLOAT64_C( 39.01), SIMDE_FLOAT64_C( 346.63)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 497.31), SIMDE_FLOAT64_C( -297.45), @@ -3294,7 +3294,7 @@ test_simde_mm512_atan2_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m512 a; simde__m512 b; simde__m512 r; - } test_vec[9] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[9] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -450.67), SIMDE_FLOAT32_C( 687.09), SIMDE_FLOAT32_C( -212.54), SIMDE_FLOAT32_C( -660.80), SIMDE_FLOAT32_C( 28.47), SIMDE_FLOAT32_C( -923.64), SIMDE_FLOAT32_C( -860.95), SIMDE_FLOAT32_C( 696.87), SIMDE_FLOAT32_C( -686.13), SIMDE_FLOAT32_C( 571.46), SIMDE_FLOAT32_C( 422.21), SIMDE_FLOAT32_C( 467.76), @@ -3421,7 +3421,7 @@ test_simde_mm512_mask_atan2_ps(SIMDE_MUNIT_TEST_ARGS) { simde__m512 a; simde__m512 b; simde__m512 r; - } test_vec[9] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[9] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( 655.87), SIMDE_FLOAT32_C( -263.99), SIMDE_FLOAT32_C( -770.35), SIMDE_FLOAT32_C( 380.46), SIMDE_FLOAT32_C( 28.08), SIMDE_FLOAT32_C( -450.67), SIMDE_FLOAT32_C( 261.31), SIMDE_FLOAT32_C( -660.80), SIMDE_FLOAT32_C( -384.03), SIMDE_FLOAT32_C( -860.95), SIMDE_FLOAT32_C( -678.17), SIMDE_FLOAT32_C( 571.46), @@ -3591,7 +3591,7 @@ test_simde_mm512_atan2_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512d a; simde__m512d b; simde__m512d r; - } test_vec[9] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[9] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -686.13), SIMDE_FLOAT64_C( 571.46), SIMDE_FLOAT64_C( 422.21), SIMDE_FLOAT64_C( 467.76), SIMDE_FLOAT64_C( 670.24), SIMDE_FLOAT64_C( 34.06), @@ -3719,7 +3719,7 @@ test_simde_mm512_mask_atan2_pd(SIMDE_MUNIT_TEST_ARGS) { simde__m512d a; simde__m512d b; simde__m512d r; - } test_vec[9] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[9] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -384.03), SIMDE_FLOAT64_C( -860.95), SIMDE_FLOAT64_C( -678.17), SIMDE_FLOAT64_C( 571.46), SIMDE_FLOAT64_C( -269.45), SIMDE_FLOAT64_C( 670.24), @@ -3952,7 +3952,7 @@ test_simde_mm256_atanh_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 0.50), SIMDE_FLOAT32_C( 0.67), SIMDE_FLOAT32_C( -0.30), SIMDE_FLOAT32_C( 0.03), SIMDE_FLOAT32_C( -0.19), SIMDE_FLOAT32_C( 0.04), @@ -4032,7 +4032,7 @@ test_simde_mm256_atanh_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -0.19), SIMDE_FLOAT64_C( 0.04), SIMDE_FLOAT64_C( -0.75), SIMDE_FLOAT64_C( 0.35)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -0.19), SIMDE_FLOAT64_C( 0.04), @@ -4080,7 +4080,7 @@ test_simde_mm512_atanh_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( 0.16), SIMDE_FLOAT32_C( 0.16), SIMDE_FLOAT32_C( 0.54), SIMDE_FLOAT32_C( 0.78), SIMDE_FLOAT32_C( 0.91), SIMDE_FLOAT32_C( 0.71), SIMDE_FLOAT32_C( 0.36), SIMDE_FLOAT32_C( 0.73), SIMDE_FLOAT32_C( 0.75), SIMDE_FLOAT32_C( 0.83), SIMDE_FLOAT32_C( 0.35), SIMDE_FLOAT32_C( 0.52), @@ -4162,7 +4162,7 @@ test_simde_mm512_mask_atanh_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( 0.27), SIMDE_FLOAT32_C( 0.84), SIMDE_FLOAT32_C( 0.39), SIMDE_FLOAT32_C( 0.17), SIMDE_FLOAT32_C( 0.51), SIMDE_FLOAT32_C( 0.04), SIMDE_FLOAT32_C( 0.07), SIMDE_FLOAT32_C( 0.85), SIMDE_FLOAT32_C( 0.16), SIMDE_FLOAT32_C( 0.78), SIMDE_FLOAT32_C( 0.71), SIMDE_FLOAT32_C( 0.73), @@ -4282,7 +4282,7 @@ test_simde_mm512_atanh_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 0.50), SIMDE_FLOAT64_C( 0.67), SIMDE_FLOAT64_C( -0.30), SIMDE_FLOAT64_C( 0.03), SIMDE_FLOAT64_C( -0.19), SIMDE_FLOAT64_C( 0.04), @@ -4364,7 +4364,7 @@ test_simde_mm512_mask_atanh_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -0.69), SIMDE_FLOAT64_C( 0.57), SIMDE_FLOAT64_C( 0.42), SIMDE_FLOAT64_C( 0.47), SIMDE_FLOAT64_C( 0.67), SIMDE_FLOAT64_C( 0.03), @@ -5751,7 +5751,7 @@ test_simde_mm256_cos_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 497.31), SIMDE_FLOAT32_C( 670.24), SIMDE_FLOAT32_C( -297.45), SIMDE_FLOAT32_C( 34.06), SIMDE_FLOAT32_C( -186.21), SIMDE_FLOAT32_C( 39.01), @@ -5831,7 +5831,7 @@ test_simde_mm256_cos_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -186.21), SIMDE_FLOAT64_C( 39.01), SIMDE_FLOAT64_C( -754.38), SIMDE_FLOAT64_C( 346.63)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -0.66), SIMDE_FLOAT64_C( 0.26), @@ -6357,7 +6357,7 @@ test_simde_mm512_cos_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -678.17), SIMDE_FLOAT32_C( -686.13), SIMDE_FLOAT32_C( 84.77), SIMDE_FLOAT32_C( 571.46), SIMDE_FLOAT32_C( 825.53), SIMDE_FLOAT32_C( 422.21), SIMDE_FLOAT32_C( -269.45), SIMDE_FLOAT32_C( 467.76), SIMDE_FLOAT32_C( 497.31), SIMDE_FLOAT32_C( 670.24), SIMDE_FLOAT32_C( -297.45), SIMDE_FLOAT32_C( 34.06), @@ -6439,7 +6439,7 @@ test_simde_mm512_mask_cos_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -450.67), SIMDE_FLOAT32_C( 687.09), SIMDE_FLOAT32_C( -212.54), SIMDE_FLOAT32_C( -660.80), SIMDE_FLOAT32_C( 28.47), SIMDE_FLOAT32_C( -923.64), SIMDE_FLOAT32_C( -860.95), SIMDE_FLOAT32_C( 696.87), SIMDE_FLOAT32_C( -686.13), SIMDE_FLOAT32_C( 571.46), SIMDE_FLOAT32_C( 422.21), SIMDE_FLOAT32_C( 467.76), @@ -6559,7 +6559,7 @@ test_simde_mm512_cos_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 497.31), SIMDE_FLOAT64_C( 670.24), SIMDE_FLOAT64_C( -297.45), SIMDE_FLOAT64_C( 34.06), SIMDE_FLOAT64_C( -186.21), SIMDE_FLOAT64_C( 39.01), @@ -6641,7 +6641,7 @@ test_simde_mm512_mask_cos_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -686.13), SIMDE_FLOAT64_C( 571.46), SIMDE_FLOAT64_C( 422.21), SIMDE_FLOAT64_C( 467.76), SIMDE_FLOAT64_C( 670.24), SIMDE_FLOAT64_C( 34.06), @@ -6825,7 +6825,7 @@ test_simde_mm256_cosd_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 497.31), SIMDE_FLOAT32_C( 670.24), SIMDE_FLOAT32_C( -297.45), SIMDE_FLOAT32_C( 34.06), SIMDE_FLOAT32_C( -186.21), SIMDE_FLOAT32_C( 39.01), @@ -6905,7 +6905,7 @@ test_simde_mm256_cosd_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -186.21), SIMDE_FLOAT64_C( 39.01), SIMDE_FLOAT64_C( -754.38), SIMDE_FLOAT64_C( 346.63)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -0.99), SIMDE_FLOAT64_C( 0.78), @@ -6953,7 +6953,7 @@ test_simde_mm512_cosd_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -678.17), SIMDE_FLOAT32_C( -686.13), SIMDE_FLOAT32_C( 84.77), SIMDE_FLOAT32_C( 571.46), SIMDE_FLOAT32_C( 825.53), SIMDE_FLOAT32_C( 422.21), SIMDE_FLOAT32_C( -269.45), SIMDE_FLOAT32_C( 467.76), SIMDE_FLOAT32_C( 497.31), SIMDE_FLOAT32_C( 670.24), SIMDE_FLOAT32_C( -297.45), SIMDE_FLOAT32_C( 34.06), @@ -7035,7 +7035,7 @@ test_simde_mm512_mask_cosd_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -450.67), SIMDE_FLOAT32_C( 687.09), SIMDE_FLOAT32_C( -212.54), SIMDE_FLOAT32_C( -660.80), SIMDE_FLOAT32_C( 28.47), SIMDE_FLOAT32_C( -923.64), SIMDE_FLOAT32_C( -860.95), SIMDE_FLOAT32_C( 696.87), SIMDE_FLOAT32_C( -686.13), SIMDE_FLOAT32_C( 571.46), SIMDE_FLOAT32_C( 422.21), SIMDE_FLOAT32_C( 467.76), @@ -7155,7 +7155,7 @@ test_simde_mm512_cosd_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 497.31), SIMDE_FLOAT64_C( 670.24), SIMDE_FLOAT64_C( -297.45), SIMDE_FLOAT64_C( 34.06), SIMDE_FLOAT64_C( -186.21), SIMDE_FLOAT64_C( 39.01), @@ -7237,7 +7237,7 @@ test_simde_mm512_mask_cosd_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -686.13), SIMDE_FLOAT64_C( 571.46), SIMDE_FLOAT64_C( 422.21), SIMDE_FLOAT64_C( 467.76), SIMDE_FLOAT64_C( 670.24), SIMDE_FLOAT64_C( 34.06), @@ -7422,7 +7422,7 @@ test_simde_mm256_cosh_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 7.24), SIMDE_FLOAT32_C( 8.19), SIMDE_FLOAT32_C( 2.86), SIMDE_FLOAT32_C( 4.69), SIMDE_FLOAT32_C( 3.48), SIMDE_FLOAT32_C( 4.71), @@ -7502,7 +7502,7 @@ test_simde_mm256_cosh_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 1.44), SIMDE_FLOAT64_C( 2.12), SIMDE_FLOAT64_C( -0.26), SIMDE_FLOAT64_C( 3.04)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 2.23), SIMDE_FLOAT64_C( 4.23), @@ -7550,7 +7550,7 @@ test_simde_mm512_cosh_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( 0.77), SIMDE_FLOAT32_C( 0.73), SIMDE_FLOAT32_C( 4.97), SIMDE_FLOAT32_C( 7.64), SIMDE_FLOAT32_C( 9.04), SIMDE_FLOAT32_C( 6.82), SIMDE_FLOAT32_C( 3.02), SIMDE_FLOAT32_C( 7.07), SIMDE_FLOAT32_C( 7.24), SIMDE_FLOAT32_C( 8.19), SIMDE_FLOAT32_C( 2.86), SIMDE_FLOAT32_C( 4.69), @@ -7632,7 +7632,7 @@ test_simde_mm512_mask_cosh_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( 2.02), SIMDE_FLOAT32_C( 8.28), SIMDE_FLOAT32_C( 3.33), SIMDE_FLOAT32_C( 0.87), SIMDE_FLOAT32_C( 4.66), SIMDE_FLOAT32_C( -0.58), SIMDE_FLOAT32_C( -0.24), SIMDE_FLOAT32_C( 8.33), SIMDE_FLOAT32_C( 0.73), SIMDE_FLOAT32_C( 7.64), SIMDE_FLOAT32_C( 6.82), SIMDE_FLOAT32_C( 7.07), @@ -7752,7 +7752,7 @@ test_simde_mm512_cosh_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 3.49), SIMDE_FLOAT64_C( 4.01), SIMDE_FLOAT64_C( 1.11), SIMDE_FLOAT64_C( 2.10), SIMDE_FLOAT64_C( 1.44), SIMDE_FLOAT64_C( 2.12), @@ -7834,7 +7834,7 @@ test_simde_mm512_mask_cosh_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -0.06), SIMDE_FLOAT64_C( 3.71), SIMDE_FLOAT64_C( 3.27), SIMDE_FLOAT64_C( 3.40), SIMDE_FLOAT64_C( 4.01), SIMDE_FLOAT64_C( 2.10), @@ -8753,7 +8753,7 @@ test_simde_mm256_div_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C( -27), INT8_C( 46), INT8_C(-122), INT8_C( 87), INT8_C( 34), INT8_C( -53), INT8_C( 64), INT8_C( -70), INT8_C( 25), INT8_C( -17), INT8_C( 56), INT8_C( 3), @@ -8962,7 +8962,7 @@ test_simde_mm256_div_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi16(INT16_C(-29867), INT16_C( 9314), INT16_C( 7980), INT16_C( 8102), INT16_C(-24663), INT16_C( 4367), INT16_C(-15443), INT16_C( -5657), INT16_C(-20080), INT16_C(-10092), INT16_C(-31734), INT16_C( 6262), @@ -9075,7 +9075,7 @@ test_simde_mm256_div_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C( 1220357195), INT32_C( 1053623553), INT32_C( 1487300768), INT32_C(-1113593972), INT32_C( -270466921), INT32_C( 1339961381), INT32_C( 586340423), INT32_C( 1641199948)), simde_mm256_set_epi32(INT32_C( 119685834), INT32_C( 18), INT32_C( 13175516), INT32_C( 2634495), @@ -9140,7 +9140,7 @@ test_simde_mm256_div_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C(-3334573923423752375), INT64_C( 5523377417165557950), INT64_C( 8907494989684855351), INT64_C(-7237415305059575746)), simde_mm256_set_epi64x(INT64_C( -9171626596647), INT64_C( -528646059918), @@ -9205,7 +9205,7 @@ test_simde_mm256_div_epu8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm256_set_epu8(UINT8_C(236), UINT8_C(194), UINT8_C(120), UINT8_C( 0), UINT8_C(238), UINT8_C(197), UINT8_C(223), UINT8_C( 50), UINT8_C(177), UINT8_C( 51), UINT8_C( 14), UINT8_C(208), @@ -9414,7 +9414,7 @@ test_simde_mm256_div_epu16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm256_set_epu16(UINT16_C( 50042), UINT16_C( 33648), UINT16_C( 7535), UINT16_C( 12279), UINT16_C( 36071), UINT16_C( 18107), UINT16_C( 48674), UINT16_C( 48206), UINT16_C( 9011), UINT16_C( 45275), UINT16_C( 7845), UINT16_C( 54048), @@ -9527,7 +9527,7 @@ test_simde_mm256_div_epu32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm256_set_epu32(UINT32_C( 621216267), UINT32_C(2973447507), UINT32_C(1814279233), UINT32_C(3673557536), UINT32_C(4015780858), UINT32_C(1070914538), UINT32_C(2707640519), UINT32_C(3041291274)), simde_x_mm256_set_epu32(UINT32_C( 122731), UINT32_C( 51630147), UINT32_C( 152670), UINT32_C( 7731229), @@ -9592,7 +9592,7 @@ test_simde_mm256_div_epu64(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm256_set_epu64x(UINT64_C(10385902570114433083), UINT64_C(14228451038995253976), UINT64_C( 3524803476344021799), UINT64_C( 9008088981795720991)), simde_x_mm256_set_epu64x(UINT64_C( 11435629647830), UINT64_C( 134705148152), @@ -9657,7 +9657,7 @@ test_simde_mm512_div_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( 114), INT8_C( 89), INT8_C( 1), INT8_C( 122), INT8_C( 12), INT8_C( 107), INT8_C( 92), INT8_C(-102), INT8_C( -63), INT8_C( 120), INT8_C( 107), INT8_C( -43), @@ -10058,7 +10058,7 @@ test_simde_mm512_div_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi16(INT16_C(-20040), INT16_C( 8356), INT16_C(-32332), INT16_C( 10333), INT16_C( -5915), INT16_C( 26879), INT16_C( 2532), INT16_C( 21861), INT16_C(-27724), INT16_C(-13980), INT16_C(-30566), INT16_C(-12851), @@ -10267,7 +10267,7 @@ test_simde_mm512_div_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C(-1425964510), INT32_C( 1884851068), INT32_C( -245085200), INT32_C( 312441627), INT32_C( 1361020823), INT32_C( -269027644), INT32_C( 2046290516), INT32_C( 253262419), INT32_C(-1435031175), INT32_C( -983397284), INT32_C( 1158205006), INT32_C( 2142968427), @@ -10382,7 +10382,7 @@ test_simde_mm512_mask_div_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( 691121094), INT32_C( 674034227), INT32_C(-1965434887), INT32_C( -920286947), INT32_C( -374673026), INT32_C(-1240805178), INT32_C( 1568850865), INT32_C(-1142977539), INT32_C(-1079516608), INT32_C( -708153743), INT32_C( 1508722402), INT32_C(-2074345640), @@ -10535,7 +10535,7 @@ test_simde_mm512_div_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C(-7120494377185439159), INT64_C( 5095015079852768951), INT64_C( -719755322986504865), INT64_C( 1195398499335632561), INT64_C( 4232475372952240435), INT64_C(-1117570177728981140), @@ -10648,7 +10648,7 @@ test_simde_mm512_div_epu8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu8(UINT8_C( 41), UINT8_C( 49), UINT8_C(171), UINT8_C(198), UINT8_C( 40), UINT8_C( 44), UINT8_C(242), UINT8_C( 51), UINT8_C(138), UINT8_C(217), UINT8_C(215), UINT8_C(249), @@ -11049,7 +11049,7 @@ test_simde_mm512_div_epu16(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu16(UINT16_C( 10545), UINT16_C( 43974), UINT16_C( 10284), UINT16_C( 62003), UINT16_C( 35545), UINT16_C( 55289), UINT16_C( 51493), UINT16_C( 35101), UINT16_C( 59818), UINT16_C( 61822), UINT16_C( 46602), UINT16_C( 53446), @@ -11258,7 +11258,7 @@ test_simde_mm512_div_epu32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu32(UINT32_C( 691121094), UINT32_C( 674034227), UINT32_C(2329532409), UINT32_C(3374680349), UINT32_C(3920294270), UINT32_C(3054162118), UINT32_C(1568850865), UINT32_C(3151989757), UINT32_C(3215450688), UINT32_C(3586813553), UINT32_C(1508722402), UINT32_C(2220621656), @@ -11373,7 +11373,7 @@ test_simde_mm512_mask_div_epu32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu32(UINT32_C( 691121094), UINT32_C( 674034227), UINT32_C(2329532409), UINT32_C(3374680349), UINT32_C(3920294270), UINT32_C(3054162118), UINT32_C(1568850865), UINT32_C(3151989757), UINT32_C(3215450688), UINT32_C(3586813553), UINT32_C(1508722402), UINT32_C(2220621656), @@ -11526,7 +11526,7 @@ test_simde_mm512_div_epu64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu64(UINT64_C( 2968342496979776051), UINT64_C(10005265515001776413), UINT64_C(16837535683400356038), UINT64_C( 6738163160628300797), UINT64_C(13810255550447513201), UINT64_C( 6479913377553186648), @@ -15516,7 +15516,7 @@ test_simde_mm256_idivrem_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i b; simde__m256i rem; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C(-1079516608), INT32_C( -708153743), INT32_C( 1508722402), INT32_C(-2074345640), INT32_C( 1747596798), INT32_C(-2063703989), INT32_C( 527472553), INT32_C(-1403096998)), simde_mm256_set_epi32(INT32_C( 172780273), INT32_C( 168508556), INT32_C( -491358722), INT32_C( -230071737), @@ -16919,7 +16919,7 @@ test_simde_mm256_log_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 7486.55), SIMDE_FLOAT32_C( 8351.20), SIMDE_FLOAT32_C( 3512.77), SIMDE_FLOAT32_C( 5170.29), SIMDE_FLOAT32_C( 4068.94), SIMDE_FLOAT32_C( 5195.06), @@ -16999,7 +16999,7 @@ test_simde_mm256_log_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 4068.94), SIMDE_FLOAT64_C( 5195.06), SIMDE_FLOAT64_C( 1228.12), SIMDE_FLOAT64_C( 6733.16)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 8.31), SIMDE_FLOAT64_C( 8.56), @@ -17047,7 +17047,7 @@ test_simde_mm512_log_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( 1609.14), SIMDE_FLOAT32_C( 1569.36), SIMDE_FLOAT32_C( 5423.87), SIMDE_FLOAT32_C( 7857.29), SIMDE_FLOAT32_C( 9127.65), SIMDE_FLOAT32_C( 7111.03), SIMDE_FLOAT32_C( 3652.77), SIMDE_FLOAT32_C( 7338.80), SIMDE_FLOAT32_C( 7486.55), SIMDE_FLOAT32_C( 8351.20), SIMDE_FLOAT32_C( 3512.77), SIMDE_FLOAT32_C( 5170.29), @@ -17129,7 +17129,7 @@ test_simde_mm512_mask_log_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( 2746.67), SIMDE_FLOAT32_C( 8435.45), SIMDE_FLOAT32_C( 3937.29), SIMDE_FLOAT32_C( 1696.00), SIMDE_FLOAT32_C( 5142.35), SIMDE_FLOAT32_C( 381.82), SIMDE_FLOAT32_C( 695.25), SIMDE_FLOAT32_C( 8484.34), SIMDE_FLOAT32_C( 1569.36), SIMDE_FLOAT32_C( 7857.29), SIMDE_FLOAT32_C( 7111.03), SIMDE_FLOAT32_C( 7338.80), @@ -17249,7 +17249,7 @@ test_simde_mm512_log_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 7486.55), SIMDE_FLOAT64_C( 8351.20), SIMDE_FLOAT64_C( 3512.77), SIMDE_FLOAT64_C( 5170.29), SIMDE_FLOAT64_C( 4068.94), SIMDE_FLOAT64_C( 5195.06), @@ -17331,7 +17331,7 @@ test_simde_mm512_mask_log_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 1569.36), SIMDE_FLOAT64_C( 7857.29), SIMDE_FLOAT64_C( 7111.03), SIMDE_FLOAT64_C( 7338.80), SIMDE_FLOAT64_C( 8351.20), SIMDE_FLOAT64_C( 5170.29), @@ -18471,7 +18471,7 @@ test_simde_mm256_log10_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 7486.55), SIMDE_FLOAT32_C( 8351.20), SIMDE_FLOAT32_C( 3512.77), SIMDE_FLOAT32_C( 5170.29), SIMDE_FLOAT32_C( 4068.94), SIMDE_FLOAT32_C( 5195.06), @@ -18551,7 +18551,7 @@ test_simde_mm256_log10_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 4068.94), SIMDE_FLOAT64_C( 5195.06), SIMDE_FLOAT64_C( 1228.12), SIMDE_FLOAT64_C( 6733.16)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 3.61), SIMDE_FLOAT64_C( 3.72), @@ -18599,7 +18599,7 @@ test_simde_mm512_log10_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( 1609.14), SIMDE_FLOAT32_C( 1569.36), SIMDE_FLOAT32_C( 5423.87), SIMDE_FLOAT32_C( 7857.29), SIMDE_FLOAT32_C( 9127.65), SIMDE_FLOAT32_C( 7111.03), SIMDE_FLOAT32_C( 3652.77), SIMDE_FLOAT32_C( 7338.80), SIMDE_FLOAT32_C( 7486.55), SIMDE_FLOAT32_C( 8351.20), SIMDE_FLOAT32_C( 3512.77), SIMDE_FLOAT32_C( 5170.29), @@ -18681,7 +18681,7 @@ test_simde_mm512_mask_log10_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( 2746.67), SIMDE_FLOAT32_C( 8435.45), SIMDE_FLOAT32_C( 3937.29), SIMDE_FLOAT32_C( 1696.00), SIMDE_FLOAT32_C( 5142.35), SIMDE_FLOAT32_C( 381.82), SIMDE_FLOAT32_C( 695.25), SIMDE_FLOAT32_C( 8484.34), SIMDE_FLOAT32_C( 1569.36), SIMDE_FLOAT32_C( 7857.29), SIMDE_FLOAT32_C( 7111.03), SIMDE_FLOAT32_C( 7338.80), @@ -18801,7 +18801,7 @@ test_simde_mm512_log10_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 7486.55), SIMDE_FLOAT64_C( 8351.20), SIMDE_FLOAT64_C( 3512.77), SIMDE_FLOAT64_C( 5170.29), SIMDE_FLOAT64_C( 4068.94), SIMDE_FLOAT64_C( 5195.06), @@ -18883,7 +18883,7 @@ test_simde_mm512_mask_log10_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 1569.36), SIMDE_FLOAT64_C( 7857.29), SIMDE_FLOAT64_C( 7111.03), SIMDE_FLOAT64_C( 7338.80), SIMDE_FLOAT64_C( 8351.20), SIMDE_FLOAT64_C( 5170.29), @@ -20962,7 +20962,7 @@ test_simde_mm256_rem_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi8(INT8_C( -65), INT8_C( -89), INT8_C( -30), INT8_C( 64), INT8_C( -43), INT8_C( -54), INT8_C( 110), INT8_C( 113), INT8_C( 89), INT8_C( -19), INT8_C( 70), INT8_C( -30), @@ -21171,7 +21171,7 @@ test_simde_mm256_rem_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi16(INT16_C(-16473), INT16_C( -7616), INT16_C(-10806), INT16_C( 28273), INT16_C( 23021), INT16_C( 18146), INT16_C(-31653), INT16_C( -168), INT16_C( 26666), INT16_C( 13822), INT16_C(-31490), INT16_C( 24651), @@ -21284,7 +21284,7 @@ test_simde_mm256_rem_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi32(INT32_C(-1079516608), INT32_C( -708153743), INT32_C( 1508722402), INT32_C(-2074345640), INT32_C( 1747596798), INT32_C(-2063703989), INT32_C( 527472553), INT32_C(-1403096998)), simde_mm256_set_epi32(INT32_C( 691121094), INT32_C( 674034227), INT32_C(-1965434887), INT32_C( -920286947), @@ -21349,7 +21349,7 @@ test_simde_mm256_rem_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_epi64x(INT64_C(-4636488523262038415), INT64_C( 6479913377553186648), INT64_C( 7505871096235581515), INT64_C( 2265477367564496986)), simde_mm256_set_epi64x(INT64_C( 2968342496979776051), INT64_C(-8441478558707775203), @@ -21414,7 +21414,7 @@ test_simde_mm256_rem_epu8(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm256_set_epu8(UINT8_C(191), UINT8_C(167), UINT8_C(226), UINT8_C( 64), UINT8_C(213), UINT8_C(202), UINT8_C(110), UINT8_C(113), UINT8_C( 89), UINT8_C(237), UINT8_C( 70), UINT8_C(226), @@ -21623,7 +21623,7 @@ test_simde_mm256_rem_epu16(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm256_set_epu16(UINT16_C( 49063), UINT16_C( 57920), UINT16_C( 54730), UINT16_C( 28273), UINT16_C( 23021), UINT16_C( 18146), UINT16_C( 33883), UINT16_C( 65368), UINT16_C( 26666), UINT16_C( 13822), UINT16_C( 34046), UINT16_C( 24651), @@ -21736,7 +21736,7 @@ test_simde_mm256_rem_epu32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm256_set_epu32(UINT32_C(3215450688), UINT32_C(3586813553), UINT32_C(1508722402), UINT32_C(2220621656), UINT32_C(1747596798), UINT32_C(2231263307), UINT32_C( 527472553), UINT32_C(2891870298)), simde_x_mm256_set_epu32(UINT32_C( 691121094), UINT32_C( 674034227), UINT32_C(2329532409), UINT32_C(3374680349), @@ -21803,7 +21803,7 @@ test_simde_mm512_mask_rem_epu32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu32(UINT32_C( 691121094), UINT32_C( 674034227), UINT32_C(2329532409), UINT32_C(3374680349), UINT32_C(3920294270), UINT32_C(3054162118), UINT32_C(1568850865), UINT32_C(3151989757), UINT32_C(3215450688), UINT32_C(3586813553), UINT32_C(1508722402), UINT32_C(2220621656), @@ -21956,7 +21956,7 @@ test_simde_mm256_rem_epu64(SIMDE_MUNIT_TEST_ARGS) { simde__m256i a; simde__m256i b; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm256_set_epu64x(UINT64_C(13810255550447513201), UINT64_C( 6479913377553186648), UINT64_C( 7505871096235581515), UINT64_C( 2265477367564496986)), simde_x_mm256_set_epu64x(UINT64_C( 2968342496979776051), UINT64_C(10005265515001776413), @@ -22021,7 +22021,7 @@ test_simde_mm512_rem_epi8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi8(INT8_C( 41), INT8_C( 49), INT8_C( -85), INT8_C( -58), INT8_C( 40), INT8_C( 44), INT8_C( -14), INT8_C( 51), INT8_C(-118), INT8_C( -39), INT8_C( -41), INT8_C( -7), @@ -22422,7 +22422,7 @@ test_simde_mm512_rem_epi16(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi16(INT16_C( 10545), INT16_C(-21562), INT16_C( 10284), INT16_C( -3533), INT16_C(-29991), INT16_C(-10247), INT16_C(-14043), INT16_C(-30435), INT16_C( -5718), INT16_C( -3714), INT16_C(-18934), INT16_C(-12090), @@ -22631,7 +22631,7 @@ test_simde_mm512_rem_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( 691121094), INT32_C( 674034227), INT32_C(-1965434887), INT32_C( -920286947), INT32_C( -374673026), INT32_C(-1240805178), INT32_C( 1568850865), INT32_C(-1142977539), INT32_C(-1079516608), INT32_C( -708153743), INT32_C( 1508722402), INT32_C(-2074345640), @@ -22746,7 +22746,7 @@ test_simde_mm512_mask_rem_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi32(INT32_C( 691121094), INT32_C( 674034227), INT32_C(-1965434887), INT32_C( -920286947), INT32_C( -374673026), INT32_C(-1240805178), INT32_C( 1568850865), INT32_C(-1142977539), INT32_C(-1079516608), INT32_C( -708153743), INT32_C( 1508722402), INT32_C(-2074345640), @@ -22899,7 +22899,7 @@ test_simde_mm512_rem_epi64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_epi64(INT64_C( 2968342496979776051), INT64_C(-8441478558707775203), INT64_C(-1609208390309195578), INT64_C( 6738163160628300797), INT64_C(-4636488523262038415), INT64_C( 6479913377553186648), @@ -23012,7 +23012,7 @@ test_simde_mm512_rem_epu8(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu8(UINT8_C( 41), UINT8_C( 49), UINT8_C(171), UINT8_C(198), UINT8_C( 40), UINT8_C( 44), UINT8_C(242), UINT8_C( 51), UINT8_C(138), UINT8_C(217), UINT8_C(215), UINT8_C(249), @@ -23413,7 +23413,7 @@ test_simde_mm512_rem_epu16(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu16(UINT16_C( 10545), UINT16_C( 43974), UINT16_C( 10284), UINT16_C( 62003), UINT16_C( 35545), UINT16_C( 55289), UINT16_C( 51493), UINT16_C( 35101), UINT16_C( 59818), UINT16_C( 61822), UINT16_C( 46602), UINT16_C( 53446), @@ -23622,7 +23622,7 @@ test_simde_mm512_rem_epu32(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu32(UINT32_C( 691121094), UINT32_C( 674034227), UINT32_C(2329532409), UINT32_C(3374680349), UINT32_C(3920294270), UINT32_C(3054162118), UINT32_C(1568850865), UINT32_C(3151989757), UINT32_C(3215450688), UINT32_C(3586813553), UINT32_C(1508722402), UINT32_C(2220621656), @@ -23735,7 +23735,7 @@ test_simde_mm512_rem_epu64(SIMDE_MUNIT_TEST_ARGS) { simde__m512i a; simde__m512i b; simde__m512i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm512_set_epu64(UINT64_C( 2968342496979776051), UINT64_C(10005265515001776413), UINT64_C(16837535683400356038), UINT64_C( 6738163160628300797), UINT64_C(13810255550447513201), UINT64_C( 6479913377553186648), @@ -24571,7 +24571,7 @@ test_simde_mm256_sin_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 497.31), SIMDE_FLOAT32_C( 670.24), SIMDE_FLOAT32_C( -297.45), SIMDE_FLOAT32_C( 34.06), SIMDE_FLOAT32_C( -186.21), SIMDE_FLOAT32_C( 39.01), @@ -24651,7 +24651,7 @@ test_simde_mm256_sin_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -186.21), SIMDE_FLOAT64_C( 39.01), SIMDE_FLOAT64_C( -754.38), SIMDE_FLOAT64_C( 346.63)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 0.76), SIMDE_FLOAT64_C( 0.97), @@ -24699,7 +24699,7 @@ test_simde_mm512_sin_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -678.17), SIMDE_FLOAT32_C( -686.13), SIMDE_FLOAT32_C( 84.77), SIMDE_FLOAT32_C( 571.46), SIMDE_FLOAT32_C( 825.53), SIMDE_FLOAT32_C( 422.21), SIMDE_FLOAT32_C( -269.45), SIMDE_FLOAT32_C( 467.76), SIMDE_FLOAT32_C( 497.31), SIMDE_FLOAT32_C( 670.24), SIMDE_FLOAT32_C( -297.45), SIMDE_FLOAT32_C( 34.06), @@ -24781,7 +24781,7 @@ test_simde_mm512_mask_sin_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -450.67), SIMDE_FLOAT32_C( 687.09), SIMDE_FLOAT32_C( -212.54), SIMDE_FLOAT32_C( -660.80), SIMDE_FLOAT32_C( 28.47), SIMDE_FLOAT32_C( -923.64), SIMDE_FLOAT32_C( -860.95), SIMDE_FLOAT32_C( 696.87), SIMDE_FLOAT32_C( -686.13), SIMDE_FLOAT32_C( 571.46), SIMDE_FLOAT32_C( 422.21), SIMDE_FLOAT32_C( 467.76), @@ -24901,7 +24901,7 @@ test_simde_mm512_sin_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 497.31), SIMDE_FLOAT64_C( 670.24), SIMDE_FLOAT64_C( -297.45), SIMDE_FLOAT64_C( 34.06), SIMDE_FLOAT64_C( -186.21), SIMDE_FLOAT64_C( 39.01), @@ -24983,7 +24983,7 @@ test_simde_mm512_mask_sin_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -686.13), SIMDE_FLOAT64_C( 571.46), SIMDE_FLOAT64_C( 422.21), SIMDE_FLOAT64_C( 467.76), SIMDE_FLOAT64_C( 670.24), SIMDE_FLOAT64_C( 34.06), @@ -25857,7 +25857,7 @@ test_simde_mm256_sind_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 497.31), SIMDE_FLOAT32_C( 670.24), SIMDE_FLOAT32_C( -297.45), SIMDE_FLOAT32_C( 34.06), SIMDE_FLOAT32_C( -186.21), SIMDE_FLOAT32_C( 39.01), @@ -25937,7 +25937,7 @@ test_simde_mm256_sind_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -186.21), SIMDE_FLOAT64_C( 39.01), SIMDE_FLOAT64_C( -754.38), SIMDE_FLOAT64_C( 346.63)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 0.11), SIMDE_FLOAT64_C( 0.63), @@ -25985,7 +25985,7 @@ test_simde_mm512_sind_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -678.17), SIMDE_FLOAT32_C( -686.13), SIMDE_FLOAT32_C( 84.77), SIMDE_FLOAT32_C( 571.46), SIMDE_FLOAT32_C( 825.53), SIMDE_FLOAT32_C( 422.21), SIMDE_FLOAT32_C( -269.45), SIMDE_FLOAT32_C( 467.76), SIMDE_FLOAT32_C( 497.31), SIMDE_FLOAT32_C( 670.24), SIMDE_FLOAT32_C( -297.45), SIMDE_FLOAT32_C( 34.06), @@ -26068,7 +26068,7 @@ test_simde_mm512_mask_sind_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -450.67), SIMDE_FLOAT32_C( 687.09), SIMDE_FLOAT32_C( -212.54), SIMDE_FLOAT32_C( -660.80), SIMDE_FLOAT32_C( 28.47), SIMDE_FLOAT32_C( -923.64), SIMDE_FLOAT32_C( -860.95), SIMDE_FLOAT32_C( 696.87), SIMDE_FLOAT32_C( -686.13), SIMDE_FLOAT32_C( 571.46), SIMDE_FLOAT32_C( 422.21), SIMDE_FLOAT32_C( 467.76), @@ -26188,7 +26188,7 @@ test_simde_mm512_sind_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 497.31), SIMDE_FLOAT64_C( 670.24), SIMDE_FLOAT64_C( -297.45), SIMDE_FLOAT64_C( 34.06), SIMDE_FLOAT64_C( -186.21), SIMDE_FLOAT64_C( 39.01), @@ -26270,7 +26270,7 @@ test_simde_mm512_mask_sind_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -686.13), SIMDE_FLOAT64_C( 571.46), SIMDE_FLOAT64_C( 422.21), SIMDE_FLOAT64_C( 467.76), SIMDE_FLOAT64_C( 670.24), SIMDE_FLOAT64_C( 34.06), @@ -26454,7 +26454,7 @@ test_simde_mm256_sinh_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 5.44), SIMDE_FLOAT32_C( 6.18), SIMDE_FLOAT32_C( 2.02), SIMDE_FLOAT32_C( 3.45), SIMDE_FLOAT32_C( 2.50), SIMDE_FLOAT32_C( 3.47), @@ -26534,7 +26534,7 @@ test_simde_mm256_sinh_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( 2.50), SIMDE_FLOAT64_C( 3.47), SIMDE_FLOAT64_C( 0.06), SIMDE_FLOAT64_C( 4.79)), simde_mm256_set_pd(SIMDE_FLOAT64_C( 6.05), SIMDE_FLOAT64_C( 16.05), @@ -26582,7 +26582,7 @@ test_simde_mm512_sinh_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( 0.38), SIMDE_FLOAT32_C( 0.35), SIMDE_FLOAT32_C( 3.66), SIMDE_FLOAT32_C( 5.76), SIMDE_FLOAT32_C( 6.85), SIMDE_FLOAT32_C( 5.12), SIMDE_FLOAT32_C( 2.14), SIMDE_FLOAT32_C( 5.31), SIMDE_FLOAT32_C( 5.44), SIMDE_FLOAT32_C( 6.18), SIMDE_FLOAT32_C( 2.02), SIMDE_FLOAT32_C( 3.45), @@ -26664,7 +26664,7 @@ test_simde_mm512_mask_sinh_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( 1.36), SIMDE_FLOAT32_C( 6.25), SIMDE_FLOAT32_C( 2.39), SIMDE_FLOAT32_C( 0.46), SIMDE_FLOAT32_C( 3.42), SIMDE_FLOAT32_C( -0.67), SIMDE_FLOAT32_C( -0.40), SIMDE_FLOAT32_C( 6.30), SIMDE_FLOAT32_C( 0.35), SIMDE_FLOAT32_C( 5.76), SIMDE_FLOAT32_C( 5.12), SIMDE_FLOAT32_C( 5.31), @@ -26784,7 +26784,7 @@ test_simde_mm512_sinh_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 5.44), SIMDE_FLOAT64_C( 6.18), SIMDE_FLOAT64_C( 2.02), SIMDE_FLOAT64_C( 3.45), SIMDE_FLOAT64_C( 2.50), SIMDE_FLOAT64_C( 3.47), @@ -26866,7 +26866,7 @@ test_simde_mm512_mask_sinh_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 0.35), SIMDE_FLOAT64_C( 5.76), SIMDE_FLOAT64_C( 5.12), SIMDE_FLOAT64_C( 5.31), SIMDE_FLOAT64_C( 6.18), SIMDE_FLOAT64_C( 3.45), @@ -28557,7 +28557,7 @@ test_simde_mm256_tan_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 497.31), SIMDE_FLOAT32_C( 670.24), SIMDE_FLOAT32_C( -297.45), SIMDE_FLOAT32_C( 34.06), SIMDE_FLOAT32_C( -186.21), SIMDE_FLOAT32_C( 39.01), @@ -28637,7 +28637,7 @@ test_simde_mm256_tan_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -186.21), SIMDE_FLOAT64_C( 39.01), SIMDE_FLOAT64_C( -754.38), SIMDE_FLOAT64_C( 346.63)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -1.15), SIMDE_FLOAT64_C( 3.76), @@ -28685,7 +28685,7 @@ test_simde_mm512_tan_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -678.17), SIMDE_FLOAT32_C( -686.13), SIMDE_FLOAT32_C( 84.77), SIMDE_FLOAT32_C( 571.46), SIMDE_FLOAT32_C( 825.53), SIMDE_FLOAT32_C( 422.21), SIMDE_FLOAT32_C( -269.45), SIMDE_FLOAT32_C( 467.76), SIMDE_FLOAT32_C( 497.31), SIMDE_FLOAT32_C( 670.24), SIMDE_FLOAT32_C( -297.45), SIMDE_FLOAT32_C( 34.06), @@ -28767,7 +28767,7 @@ test_simde_mm512_mask_tan_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -450.67), SIMDE_FLOAT32_C( 687.09), SIMDE_FLOAT32_C( -212.54), SIMDE_FLOAT32_C( -660.80), SIMDE_FLOAT32_C( 28.47), SIMDE_FLOAT32_C( -923.64), SIMDE_FLOAT32_C( -860.95), SIMDE_FLOAT32_C( 696.87), SIMDE_FLOAT32_C( -686.13), SIMDE_FLOAT32_C( 571.46), SIMDE_FLOAT32_C( 422.21), SIMDE_FLOAT32_C( 467.76), @@ -28887,7 +28887,7 @@ test_simde_mm512_tan_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 497.31), SIMDE_FLOAT64_C( 670.24), SIMDE_FLOAT64_C( -297.45), SIMDE_FLOAT64_C( 34.06), SIMDE_FLOAT64_C( -186.21), SIMDE_FLOAT64_C( 39.01), @@ -28969,7 +28969,7 @@ test_simde_mm512_mask_tan_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -686.13), SIMDE_FLOAT64_C( 571.46), SIMDE_FLOAT64_C( 422.21), SIMDE_FLOAT64_C( 467.76), SIMDE_FLOAT64_C( 670.24), SIMDE_FLOAT64_C( 34.06), @@ -29153,7 +29153,7 @@ test_simde_mm256_tand_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 497.31), SIMDE_FLOAT32_C( 670.24), SIMDE_FLOAT32_C( -297.45), SIMDE_FLOAT32_C( 34.06), SIMDE_FLOAT32_C( -186.21), SIMDE_FLOAT32_C( 39.01), @@ -29233,7 +29233,7 @@ test_simde_mm256_tand_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -186.21), SIMDE_FLOAT64_C( 39.01), SIMDE_FLOAT64_C( -754.38), SIMDE_FLOAT64_C( 346.63)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -0.11), SIMDE_FLOAT64_C( 0.81), @@ -29281,7 +29281,7 @@ test_simde_mm512_tand_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -678.17), SIMDE_FLOAT32_C( -686.13), SIMDE_FLOAT32_C( 84.77), SIMDE_FLOAT32_C( 571.46), SIMDE_FLOAT32_C( 825.53), SIMDE_FLOAT32_C( 422.21), SIMDE_FLOAT32_C( -269.45), SIMDE_FLOAT32_C( 467.76), SIMDE_FLOAT32_C( 497.31), SIMDE_FLOAT32_C( 670.24), SIMDE_FLOAT32_C( -297.45), SIMDE_FLOAT32_C( 34.06), @@ -29363,7 +29363,7 @@ test_simde_mm512_mask_tand_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -450.67), SIMDE_FLOAT32_C( 687.09), SIMDE_FLOAT32_C( -212.54), SIMDE_FLOAT32_C( -660.80), SIMDE_FLOAT32_C( 28.47), SIMDE_FLOAT32_C( -923.64), SIMDE_FLOAT32_C( -860.95), SIMDE_FLOAT32_C( 696.87), SIMDE_FLOAT32_C( -686.13), SIMDE_FLOAT32_C( 571.46), SIMDE_FLOAT32_C( 422.21), SIMDE_FLOAT32_C( 467.76), @@ -29483,7 +29483,7 @@ test_simde_mm512_tand_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 497.31), SIMDE_FLOAT64_C( 670.24), SIMDE_FLOAT64_C( -297.45), SIMDE_FLOAT64_C( 34.06), SIMDE_FLOAT64_C( -186.21), SIMDE_FLOAT64_C( 39.01), @@ -29565,7 +29565,7 @@ test_simde_mm512_mask_tand_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -686.13), SIMDE_FLOAT64_C( 571.46), SIMDE_FLOAT64_C( 422.21), SIMDE_FLOAT64_C( 467.76), SIMDE_FLOAT64_C( 670.24), SIMDE_FLOAT64_C( 34.06), @@ -30279,7 +30279,7 @@ test_simde_mm256_tanh_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256 a; simde__m256 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_ps(SIMDE_FLOAT32_C( 0.50), SIMDE_FLOAT32_C( 0.67), SIMDE_FLOAT32_C( -0.30), SIMDE_FLOAT32_C( 0.03), SIMDE_FLOAT32_C( -0.19), SIMDE_FLOAT32_C( 0.04), @@ -30359,7 +30359,7 @@ test_simde_mm256_tanh_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m256d a; simde__m256d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm256_set_pd(SIMDE_FLOAT64_C( -0.19), SIMDE_FLOAT64_C( 0.04), SIMDE_FLOAT64_C( -0.75), SIMDE_FLOAT64_C( 0.35)), simde_mm256_set_pd(SIMDE_FLOAT64_C( -0.19), SIMDE_FLOAT64_C( 0.04), @@ -30407,7 +30407,7 @@ test_simde_mm512_tanh_ps(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -0.68), SIMDE_FLOAT32_C( -0.69), SIMDE_FLOAT32_C( 0.08), SIMDE_FLOAT32_C( 0.57), SIMDE_FLOAT32_C( 0.83), SIMDE_FLOAT32_C( 0.42), SIMDE_FLOAT32_C( -0.27), SIMDE_FLOAT32_C( 0.47), SIMDE_FLOAT32_C( 0.50), SIMDE_FLOAT32_C( 0.67), SIMDE_FLOAT32_C( -0.30), SIMDE_FLOAT32_C( 0.03), @@ -30489,7 +30489,7 @@ test_simde_mm512_mask_tanh_ps(SIMDE_MUNIT_TEST_ARGS) { simde__mmask16 k; simde__m512 a; simde__m512 r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_ps(SIMDE_FLOAT32_C( -0.45), SIMDE_FLOAT32_C( 0.69), SIMDE_FLOAT32_C( -0.21), SIMDE_FLOAT32_C( -0.66), SIMDE_FLOAT32_C( 0.03), SIMDE_FLOAT32_C( -0.92), SIMDE_FLOAT32_C( -0.86), SIMDE_FLOAT32_C( 0.70), SIMDE_FLOAT32_C( -0.69), SIMDE_FLOAT32_C( 0.57), SIMDE_FLOAT32_C( 0.42), SIMDE_FLOAT32_C( 0.47), @@ -30609,7 +30609,7 @@ test_simde_mm512_tanh_pd(SIMDE_MUNIT_TEST_ARGS) { const struct { simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( 0.50), SIMDE_FLOAT64_C( 0.67), SIMDE_FLOAT64_C( -0.30), SIMDE_FLOAT64_C( 0.03), SIMDE_FLOAT64_C( -0.19), SIMDE_FLOAT64_C( 0.04), @@ -30691,7 +30691,7 @@ test_simde_mm512_mask_tanh_pd(SIMDE_MUNIT_TEST_ARGS) { simde__mmask8 k; simde__m512d a; simde__m512d r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_mm512_set_pd(SIMDE_FLOAT64_C( -0.69), SIMDE_FLOAT64_C( 0.57), SIMDE_FLOAT64_C( 0.42), SIMDE_FLOAT64_C( 0.47), SIMDE_FLOAT64_C( 0.67), SIMDE_FLOAT64_C( 0.03), @@ -30813,7 +30813,7 @@ test_simde_mm256_udivrem_epi32(SIMDE_MUNIT_TEST_ARGS) { simde__m256i b; simde__m256i rem; simde__m256i r; - } test_vec[8] = { + } SIMDE_ALIGN_REDUCE_STRUCT test_vec[8] = { { simde_x_mm256_set_epu32(UINT32_C(3215450688), UINT32_C(3586813553), UINT32_C(1508722402), UINT32_C(2220621656), UINT32_C(1747596798), UINT32_C(2231263307), UINT32_C( 527472553), UINT32_C(2891870298)), simde_x_mm256_set_epu32(UINT32_C( 172780273), UINT32_C( 168508556), UINT32_C(3803608574), UINT32_C(4064895559),