[OMNIML-5024] specdec_bench cell t0_d3 — google/gemma-4-E4B-it / MTP / vllm#1663
[OMNIML-5024] specdec_bench cell t0_d3 — google/gemma-4-E4B-it / MTP / vllm#1663ChenhanYu wants to merge 7 commits into
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Signed-off-by: Pensieve Intern <chenhany@nvidia.com>
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✨ Finishing Touches🧪 Generate unit tests (beta)
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Signed-off-by: Pensieve Intern <chenhany@nvidia.com>
Signed-off-by: Pensieve Intern <chenhany@nvidia.com>
Signed-off-by: Pensieve Intern <chenhany@nvidia.com>
Signed-off-by: Pensieve Intern <chenhany@nvidia.com>
Codecov Report✅ All modified and coverable lines are covered by tests. Additional details and impacted files@@ Coverage Diff @@
## main #1663 +/- ##
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+ Coverage 56.58% 56.59% +0.01%
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Files 507 507
Lines 55794 55794
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+ Hits 31573 31579 +6
+ Misses 24221 24215 -6
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Signed-off-by: Pensieve Intern <chenhany@nvidia.com>
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Signed-off-by: Pensieve Intern <chenhany@nvidia.com>
Adds the SPEED-bench MTP/vLLM parent YAML for google/gemma-4-E4B-it and the t0_d3 runtime_params cell.\n\nSweep: gemma-4-E4B-it_mtp_vllm_t0_d3