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[OMNIML-5024] specdec_bench cell t0_d3 — google/gemma-4-E4B-it / MTP / vllm#1663

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[OMNIML-5024] specdec_bench cell t0_d3 — google/gemma-4-E4B-it / MTP / vllm#1663
ChenhanYu wants to merge 7 commits into
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Adds the SPEED-bench MTP/vLLM parent YAML for google/gemma-4-E4B-it and the t0_d3 runtime_params cell.\n\nSweep: gemma-4-E4B-it_mtp_vllm_t0_d3

Signed-off-by: Pensieve Intern <chenhany@nvidia.com>
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Signed-off-by: Pensieve Intern <chenhany@nvidia.com>
Signed-off-by: Pensieve Intern <chenhany@nvidia.com>
Signed-off-by: Pensieve Intern <chenhany@nvidia.com>
Signed-off-by: Pensieve Intern <chenhany@nvidia.com>
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Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 56.59%. Comparing base (111b7eb) to head (6fc56ed).

Additional details and impacted files
@@            Coverage Diff             @@
##             main    #1663      +/-   ##
==========================================
+ Coverage   56.58%   56.59%   +0.01%     
==========================================
  Files         507      507              
  Lines       55794    55794              
==========================================
+ Hits        31573    31579       +6     
+ Misses      24221    24215       -6     
Flag Coverage Δ
unit 54.41% <ø> (+0.01%) ⬆️

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Signed-off-by: Pensieve Intern <chenhany@nvidia.com>
@ChenhanYu ChenhanYu force-pushed the pensieve-intern/OMNIML-5022/t0_d3 branch from ce245cd to 10d5d24 Compare June 10, 2026 00:44
Signed-off-by: Pensieve Intern <chenhany@nvidia.com>
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