[None][perf] CuTeDSL MegaMoE: eliminate per-launch workspace memset o…#15201
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[None][perf] CuTeDSL MegaMoE: eliminate per-launch workspace memset o…#15201Barry-Delaney wants to merge 1 commit into
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…verhead Two optimizations that reduce CuTeDSL MegaMoE forward latency by up to 2.7x at large token counts (DSv4 shapes, B200 8-GPU EP=8): 1. Targeted workspace zeroing: the per-launch `_zero_local_workspace_preserving_phase` was zeroing the entire ~1.2 GB local workspace (minus the 4-byte nvlink_barrier_counter). Only ~0.57 MB of atomic counters and small safety-critical data regions actually need resetting. Atomic counters (l1_arrival_count, expert_send_count, grid_sync_counter, fc1_done_counter, fc2_done_counter, load_balance_counter) must start at zero; l1_topk_weights_buffer and token_src_metadata must be zero for MMA padding rows to prevent stale data from corrupting FC2 → combine scatter. The bulk data regions (l1_token_buffer, l1_sf_buffer, fc1_output, fc1_output_sf) are overwritten by dispatch/FC1 before being read. This eliminates ~3 ms/fwd of memset at 32768T. 2. Fuse bf16->fp32 cast into sum: replace `combine_output.to(fp32).sum(dim=1)` with `combine_output.sum(dim=1, dtype=fp32)`, eliminating a full-size bf16->fp32 materialization kernel (~300 us/layer). 3. Cache `get_regions()` return value to avoid re-creating symmetric memory tensor views on every forward call, which is incompatible with CUDA-graph capture (cudaErrorStreamCaptureUnsupported). Measured (min latency, CG, balanced routing, 8×B200): 32768T: 5.78 ms -> 2.15 ms (2.69x) 16384T: 2.98 ms -> 1.16 ms (2.57x) 8192T: 1.56 ms -> 0.65 ms (2.40x) 4096T: 0.85 ms -> 0.40 ms (2.10x) Signed-off-by: Barry Kang <43644113+Barry-Delaney@users.noreply.github.com>
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…verhead
Two optimizations that reduce CuTeDSL MegaMoE forward latency by up to 2.7x at large token counts (DSv4 shapes, B200 8-GPU EP=8):
Targeted workspace zeroing: the per-launch
_zero_local_workspace_preserving_phasewas zeroing the entire ~1.2 GB local workspace (minus the 4-byte nvlink_barrier_counter). Only ~0.57 MB of atomic counters and small safety-critical data regions actually need resetting. Atomic counters (l1_arrival_count, expert_send_count, grid_sync_counter, fc1_done_counter, fc2_done_counter, load_balance_counter) must start at zero; l1_topk_weights_buffer and token_src_metadata must be zero for MMA padding rows to prevent stale data from corrupting FC2 → combine scatter. The bulk data regions (l1_token_buffer, l1_sf_buffer, fc1_output, fc1_output_sf) are overwritten by dispatch/FC1 before being read. This eliminates ~3 ms/fwd of memset at 32768T.Fuse bf16->fp32 cast into sum: replace
combine_output.to(fp32).sum(dim=1)withcombine_output.sum(dim=1, dtype=fp32), eliminating a full-size bf16->fp32 materialization kernel (~300 us/layer).Cache
get_regions()return value to avoid re-creating symmetric memory tensor views on every forward call, which is incompatible with CUDA-graph capture (cudaErrorStreamCaptureUnsupported).Measured (min latency, CG, balanced routing, 8×B200):
32768T: 5.78 ms -> 2.15 ms (2.69x)
16384T: 2.98 ms -> 1.16 ms (2.57x)
8192T: 1.56 ms -> 0.65 ms (2.40x)
4096T: 0.85 ms -> 0.40 ms (2.10x)
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