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Add an opt-in U2.2/B0/F2 UVHS flow that regenerates repository-owned Vivado IP and imports the vendor DDR IP. Keep the normal Makefile and JTAG flow unchanged, with UVHS targets isolated in uvhs.mk. Simplify generated-clock constraints and retain only the RTL and tool compatibility needed for the regenerated NutShell bitstream. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Synchronize the CPU reset into the interconnect clock domain before driving the AXI bridge reset input. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Align the kmh wrapper with current XiangShan AXI widths and isolate unused SystemJTAG and RTC crossings in the UVHS image. Detect DMA-capable SimTop builds and apply XiangShan-specific placement, routing, and generated-clock settings. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Use native-width vendor DDR DCPs and remove the NutShell AXI width adapter. Consolidate UVHS-only RTL selection while retaining the normal Vivado target behavior. Add attached runtime commands for download, reset, and DDR backdoor writes, together with tool compatibility checks and updated flow documentation. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Connect a 64-bit UVHS generalBus to the existing BRAM-backed flash through AXI_bridge and verify each raw image with a full readback. Expose standalone uvhs_* build and runtime targets while keeping the normal Vivado and JTAG commands unchanged. Make attached runtime commands report completion and propagate failures. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Instantiate the width-matched vendor DDR IP directly and keep only the address and ID adaptations required by its AXI interface. Update the runtime writemem path for the direct instance. Remove unused memory-array, auxiliary-DDR, ClockHub, and manual DDR pin branches. Inline the trivial file-list filter and document the reduced flow. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Run uv_shell as a tracked background session so uvhs_write_bitstream returns after programming while later reset and memory commands retain the database connection. Move reset sequencing and command polling out of hw_run_download.tcl into shared runtime control procedures. Reject commands without a ready session and preserve the validated reset order. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Map the UVHS GeneralBus master address space to the flash target at offset zero and issue runtime DMA transfers from the same base. Keep CPU and JTAG flash mappings at 0x10000000. This matches the validated 64-bit GeneralBus path and restores full-image readback. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Replace generated Vivado Tcl and XDC rewrites with one explicit pre-opt stage for the required XDMA refclock and CDC constraints. Keep only the Bash and runtime-library compatibility required by the validated installation. Build XiangShan from fpga-release RTL, normalize external file lists, and move the download entry point under uvhs/. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Use the FPGA release build as the sole core input and collapse external file-list generation to one output mode. Drop unused IP exports, RANDOMIZE defines, and path-forwarding knobs. Replace make/csh wrappers with inherited Bash Make flags, keep only observed shell and runtime compatibility, and document the reduced flow. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Share RTL_INCLUDE parsing between the Vivado and UVHS file-list generators while keeping each output contract independent. Generate and validate the complete UVHS input in one step. Move common Tcl helpers and automatic partitioning out of the frontend and backend drivers. Make selected-FPGA assembly state explicit and order file-list generation after all stub exports. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Add uvhs and uvhs_bitstream as the stable build entry points so upper-level callers can mirror the normal project and bitstream sequence. Keep detailed stages available for reuse and serialize the compatibility pipeline under parallel make. Document how shared RTL_INCLUDE parsing feeds the different Vivado Tcl and UVHS flat-file consumers. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Unify Vivado and UVHS file-list generation while preserving their output contracts. Fold partition setup into the backend driver and runtime command submission into the session manager. Rename board setup around topology and pin assignment, remove the redundant source-check target, and reduce UVHS tuning inputs to the validated flow controls. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Use the fully routed 70/35 LUT fill-rate pair for XiangShan and fix the validated U2.2 platform in the frontend and backend drivers. Restore update_core_flist.sh as the shared Vivado/UVHS entry point and deduplicate GeneralBus width validation without weakening cache checks. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Keep all four B0 FPGAs in the default XiangShan UVHS topology so automatic partitioning can reproduce the routed 70/35 setup. Leave NutShell on the single F2 path. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Run the frontend and backend serially from make uvhs while retaining the stage targets for debugging and reuse. Remove uvhs_bitstream and the single-F2 packaging path because multi-FPGA runtime uses the committed hw.dat database and its per-FPGA PnR outputs. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Move Vivado, generalBus, and external DDR preparation behind one helper and keep uvhs.mk focused on flow targets. Rename the retained runtime Tcl entry point to describe its command-server lifetime. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Separate compilation and runtime helpers into dedicated directories while keeping uvhs.mk as the stable entry point. Rename the shared clock file to timing.tcl and retain post-transform asynchronous clock constraints. Document the verified runtime release behavior and updated script layout. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Declare asynchronous clock groups with the primary frontend clocks so uvsyn does not optimize unrelated domains as synchronous. Reapply the same groups after UVHS clock transformation and per-FPGA Vivado linking. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Accept an opt-in probe Tcl file during frontend synthesis. Add a runtime capture command that reconstructs USDB data and converts it to VCD. Keep runtime operations in the database-owning server. Simplify file-based session dispatch and preflight checks, and deduplicate the Vivado IP run setup. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Source an empty in-tree probe script by default while retaining the external probe override. Add a runtime command to clear trigger conditions and disable capture explicitly. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Provide a fill-in probe template that preserves indexed RTL hierarchy paths. Rename waveform targets and runtime commands to the uvhs_ila interface. Expose trigger position, upload depth, and optional depth-counting clock controls. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Describe the one-shot runtime controls and the trigger-relative upload window. Record the PDDR4DME conflict observed when UHD capture and DUT DDR share the single-F2 topology. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Pin the external DDR wrapper to B0/F0/FMC0 so UHD retains the per-FPGA FMC3 cards. Keep the DDR status on F0 and localize the derived SOC clock for F0/F2 partitioning. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Let UVHS distribute SOC_GATED_CLK across the F0/F2 partition. Explicit localization creates a replicated clock cone constrained into F0 IO resources, conflicting with user DDR and Aurora clock placement. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Keep the status output with the CPU and XDMA sideband pins. Assigning it to the F0 user-DDR partition crosses the SOC clock timing group and makes transform_clock fail. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
The calibration-status output crosses the user-DDR and CPU partitions. It is not part of the functional interface, so do not bind it to either FPGA sideband connector. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Route SOC_GATED_CLK across B0/F0 and B0/F2 through the platform global clock, retaining the hard user-DDR placement and its F0 calibration-status pin without localizing clock primitives. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Drive the UVHS DDR wrapper from the ungated source while sharing the DiffTest clock enable with the CPU clock gate. Keep the CPU and DDR timing groups separate during partitioning and exclude only the expected DDR AXI local-clock TDM check. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Keep temporary and ILA output under the selected runtime work directory, and pass it explicitly to the retained UVHS session. Reapply the 25 MHz CPU debug clock before downloading a database. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Arm UHD capture separately so fpga-host can install trigger conditions\nbefore releasing the CPU and preserve a pre-trigger window. Add a\ndedicated USDB-to-VCD target and prepare writable UHD output paths.\n\nCo-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Use the supported clock_tdm check group so the expected inter-FPGA clock-domain crossings do not abort backend compilation. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Document the capture-stop pipeline tail observed with position zero so the pre-trigger guarantee matches the validated waveform. Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
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