[bsp][renesas]:support RA8P1 Titan dual-core projects

bsp/renesas/libraries/Kconfig

@@ -63,10 +63,22 @@ config SOC_SERIES_R7FA8M85
 
 config SOC_SERIES_R7KA8P1
     bool
-    select ARCH_ARM_CORTEX_M85
     select SOC_FAMILY_RENESAS_RA
     default n
 
+config SOC_SERIES_R7KA8P1_CORE0
+    bool
+    select SOC_SERIES_R7KA8P1
+    select ARCH_ARM_CORTEX_M85
+    default n
+
+config SOC_SERIES_R7KA8P1_CORE1
+    bool
+    select SOC_SERIES_R7KA8P1
+    select ARCH_ARM_CORTEX_M33
+    select ARCH_ARM_CORTEX_SECURE
+    default n
+
 config SOC_SERIES_R9A07G0
     bool
     select ARCH_ARM_CORTEX_R52

bsp/renesas/ra8p1-titan-board/.gitignore

@@ -1,26 +1,4 @@
-/RTE
-/Listings
-/Objects
-/Debug
-/build
-/makefile.targets
-/rtconfig.pyc
-/libraries
-/rt-thread
-/project.custom_argvars
-/.vscode
-/__pycache
-/settings
-/rtconfig_preinc.h
-/bsp_linker_info.h
-/fsp_gen.ld
-/memory_regions.ld
-/cmake
-/.api_xml
-/.clangd
+/build/
+/.secure_xml
 /.secure_azone
 /.secure_rzone
-/.secure_xml
-/ra_cfg.txt
-/packages/pkgs.json
-/packages/pkgs_error.json

bsp/renesas/ra8p1-titan-board/README.md

@@ -6,6 +6,13 @@
 
 This document provides the BSP (Board Support Package) description for the RT-Thread **Titan Board** development board. By following the Quick Start Guide, developers can quickly get started with this BSP and run RT-Thread on the development board.
 
+This BSP contains two independent projects:
+
+- `m85`: Cortex-M85 (CPU0), using UART8 and responsible for starting CPU1.
+- `m33`: Cortex-M33 (CPU1), using UART5 and started by CPU0.
+
+Run SCons from the corresponding core directory. Each project has its own `configuration.xml`, `ra`, `ra_cfg`, `ra_gen`, and linker scripts.
+
 The main contents include:
 
 - Introduction to the development board
@@ -19,11 +26,11 @@ Titan Board integrates the **RA8P1** chip featuring a **1GHz Arm® Cortex®-M85*
 
 The front view of the development board is shown below:
 
-![big](figures/big.png)
+![big](m85/figures/big.png)
 
 Common **on-board resources** are as follows:
 
-![titan_board_hw_resource](figures/titan_board_hw_resource.png)
+![titan_board_hw_resource](m85/figures/titan_board_hw_resource.png)
 
 ## Peripheral Support
 
@@ -77,53 +84,75 @@ This BSP can be directly imported into **RT-Thread Studio v2.3.0**. The followin
 
 1. Install the compiler toolchain:
 
-![image-20251127164450247](figures/image-20251127164450247.png)
+![image-20251127164450247](m85/figures/image-20251127164450247.png)
 
 2. Install debugging tools:
 
 Download **J-Link v8.48** and **PyOCD 0.2.9**.
 
-![image-20251127164534568](figures/image-20251127164534568.png)
+![image-20251127164534568](m85/figures/image-20251127164534568.png)
 
 ### **Create a Project**
 
 1. Click **File → Import**.
 
-![image-20251127164859503](figures/image-20251127164859503.png)
+![image-20251127164859503](m85/figures/image-20251127164859503.png)
 
 2. Select **Import RT-Thread BSP**, then click **Next**.
 
-![image-20251127164952040](figures/image-20251127164952040.png)
+![image-20251127164952040](m85/figures/image-20251127164952040.png)
 
 3. Select the BSP root directory and fill in project information, then click **Finish**.
 
-![image-20251127165319591](figures/image-20251127165319591.png)
+![image-20251127165319591](m85/figures/image-20251127165319591.png)
 
 4. The project based on the BSP is created.
 
-![image-20251127165406340](figures/image-20251127165406340.png)
+![image-20251127165406340](m85/figures/image-20251127165406340.png)
 
 ### **Configure Debug/Download Settings**
 
 > **Note: Sometimes you may need to modify the settings twice for them to take effect.**
 
 Modify the debugger configuration in the **Debugger** tab.
 
-![image-20251127165957537](figures/image-20251127165957537.png)
+![image-20251127165957537](m85/figures/image-20251127165957537.png)
 
 In the **Download** tab, change the download method to **Flash Hex File**, then click **OK**.
 
-![image-20251127170436152](figures/image-20251127170436152.png)
+![image-20251127170436152](m85/figures/image-20251127170436152.png)
 
-![image-20251127171037225](figures/image-20251127171037225.png)
+![image-20251127171037225](m85/figures/image-20251127171037225.png)
 
 **Hardware Connection**
 
 Use a USB cable to connect the development board to the PC, and use the DAP-Link interface to download and debug the program.
 
 **Build and Download**
 
-![image-20251127165554294](figures/image-20251127165554294.png)
+![image-20251127165554294](m85/figures/image-20251127165554294.png)
+
+When either the `m85` or `m33` Keil project is built, FSP Smart Configurator 6.2.0 runs after linking and generates `Objects/template.sbd`. The SBD stores the core's security and memory-region metadata for RA8P1 dual-core FSP solution partitioning and composition; it is not a directly flashable image. Only the SBD after-build step is enabled, so the build does not regenerate or overwrite the FSP-generated sources and linker scripts.
+
+After building `m85/project.uvprojx` and `m33/project.uvprojx` with Keil, run `build_solution_sbd.bat` from this BSP root. The script validates the core, device, and FSP version of both core SBDs, then uses `solution.xml` to generate `build/ra8p1_titan_dualcore.sbd`. This solution SBD is used for FSP dual-core partition and configuration exchange; it is not a directly flashable firmware image.
+
+The RA8P1 code MRAM is shared by both cores, but the J-Link Flash Algorithm must access it through CPU0/AP0, while M33 debugging must attach to CPU1/AP2. A Keil target has only one Device selection shared by its download and debug settings, so one target cannot select CPU0 for programming and CPU1 for debugging. The two M33 targets therefore share the same `Objects/template.axf`; they do not produce two M33 images.
+
+| Target | Device | Purpose |
+| --- | --- | --- |
+| `M33_Debug_CPU1` | `R7KA8P1KF:CPU1` | Build the Cortex-M33 image and attach to CPU1. Its Flash Download utility is disabled. |
+| `M33_Download_CPU0` | `R7KA8P1KF:CPU0` | Program the existing M33 AXF at `0x020C0000` through CPU0 using Keil's native J-Link Flash driver. |
+
+Run `scons --target=mdk5` from the `m33` directory to regenerate `project.uvprojx`. Both targets are defined in `template.uvprojx` and are preserved in the generated project.
+
+1. Build and download the CPU0 firmware from the `m85` Keil project.
+2. Select and build `M33_Debug_CPU1` in the `m33` project.
+3. Switch to `M33_Download_CPU0` and click Download without building this target. The J-Link log must report `R7KA8P1KF_CPU0`.
+4. Switch back to `M33_Debug_CPU1` and attach to CPU1 after programming.
+
+CPU0 starts CPU1 once from the common RA board initialization in `bsp/renesas/libraries/HAL_Drivers/drv_common.c` when `BSP_START_SECONDARY_CORE` is enabled. `hal_entry()` must not start CPU1 again.
+
+Do not use the M33 Reset command. Restart both cores with the board reset button, wait for M85 to start CPU1, and then attach again.
 
 **View Running Results**
 
@@ -209,22 +238,22 @@ Users can locate the `configuration.xml` file in the project and import it into
 
 Select **File → Open** at the top-left corner to open the configuration file.
 
-![image-20251030163423452](figures/image-20251030163423452.png)
+![image-20251030163423452](m85/figures/image-20251030163423452.png)
 
 * **Generate FSP Code:**
 
-![image-20251030163707813](figures/image-20251030163707813.png)
+![image-20251030163707813](m85/figures/image-20251030163707813.png)
 
 **RT-Thread Settings**
 
 In **RT-Thread Settings**, you can configure the RT-Thread kernel, components, software packages, and Titan Board device drivers.
 
-![image-20250819173700386](figures/image-20250819173700386.png)
+![image-20250819173700386](m85/figures/image-20250819173700386.png)
 
 ## Contact Information
 
 If you have any thoughts or suggestions during usage, please feel free to contact us via the [RT-Thread Community Forum](https://club.rt-thread.org/).
 
 ## Contribute Code
 
-If you're interested in Titan Board and have some exciting projects you'd like to share, we welcome code contributions. Please refer to [How to Contribute to RT-Thread Code](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github).
+If you're interested in Titan Board and have some exciting projects you'd like to share, we welcome code contributions. Please refer to [How to Contribute to RT-Thread Code](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github).

bsp/renesas/ra8p1-titan-board/README_zh.md

@@ -6,6 +6,13 @@
 
 本文档为 RT-Thread Titan Board 开发板提供 BSP (板级支持包) 说明。通过阅读快速上手章节，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
 
+本 BSP 包含两个相互独立的工程：
+
+- `m85`：Cortex-M85（CPU0），使用 UART8，并负责启动 CPU1。
+- `m33`：Cortex-M33（CPU1），使用 UART5，由 CPU0 启动。
+
+请进入对应核心目录运行 SCons。两个工程分别维护自己的 `configuration.xml`、`ra`、`ra_cfg`、`ra_gen` 和链接脚本。
+
 主要内容如下：
 
 - 开发板介绍
@@ -19,11 +26,11 @@ Titan Board 搭载频率 1GHz Arm® Cortex®-M85 与 250MHz Arm® Cortex®-M33 
 
 开发板正面外观如下图：
 
-![big](figures/big.png)
+![big](m85/figures/big.png)
 
 该开发板常用 **板载资源** 如下：
 
-![titan_board_hw_resource](figures/titan_board_hw_resource.png)
+![titan_board_hw_resource](m85/figures/titan_board_hw_resource.png)
 
 ## 外设支持
 
@@ -75,53 +82,75 @@ Titan Board 搭载频率 1GHz Arm® Cortex®-M85 与 250MHz Arm® Cortex®-M33 
 
 1. 安装编译工具链
 
-![image-20251127164450247](figures/image-20251127164450247.png)
+![image-20251127164450247](m85/figures/image-20251127164450247.png)
 
 2. 调试工具
 
 ​	下载 J-Link v8.48 和 PyOCD 0.2.9。
 
-![image-20251127164534568](figures/image-20251127164534568.png)
+![image-20251127164534568](m85/figures/image-20251127164534568.png)
 
 **创建工程**
 
 1. 点击左上角 文件-->导入。
 
-![image-20251127164859503](figures/image-20251127164859503.png)
+![image-20251127164859503](m85/figures/image-20251127164859503.png)
 
 2. 选择导入 RT-Thread Bsp 到工作空间，点击“下一步”。
 
-![image-20251127164952040](figures/image-20251127164952040.png)
+![image-20251127164952040](m85/figures/image-20251127164952040.png)
 
 3. 选择 BSP 根目录并填写好工程信息，点击“完成”。
 
-![image-20251127165319591](figures/image-20251127165319591.png)
+![image-20251127165319591](m85/figures/image-20251127165319591.png)
 
 4. 基于 BSP 创建工程就完成了。
 
-![image-20251127165406340](figures/image-20251127165406340.png)
+![image-20251127165406340](m85/figures/image-20251127165406340.png)
 
 **配置工程的调试下载设置**
 
 > **注意：有时需要修改两遍才生效。**
 
 在”调试器“选项卡中修改调试器的配置。
 
-![image-20251127165957537](figures/image-20251127165957537.png)
+![image-20251127165957537](m85/figures/image-20251127165957537.png)
 
 在“下载”选项卡中将烧录方式改为“烧录Hex文件”，之后点击“确定“完成配置。
 
-![image-20251127170436152](figures/image-20251127170436152.png)
+![image-20251127170436152](m85/figures/image-20251127170436152.png)
 
-![image-20251127171037225](figures/image-20251127171037225.png)
+![image-20251127171037225](m85/figures/image-20251127171037225.png)
 
 **硬件连接**
 
 使用 USB 数据线连接开发板到 PC，使用 DAP-Link 接口下载和 DEBUG 程序。
 
 **编译下载**
 
-![image-20251127165554294](figures/image-20251127165554294.png)
+![image-20251127165554294](m85/figures/image-20251127165554294.png)
+
+使用 Keil 编译 `m85` 或 `m33` 工程时，链接完成后会调用 FSP Smart Configurator 6.2.0 生成对应的 `Objects/template.sbd`。SBD 保存该核的安全区和内存区域描述，供 RA8P1 双核 FSP solution 进行分区与组合；它不是可直接烧录的固件。工程只启用 SBD 的 after-build 生成，不会在编译前覆盖 FSP 已生成的源码和链接脚本。
+
+依次使用 Keil 编译 `m85/project.uvprojx` 和 `m33/project.uvprojx` 后，在本 BSP 根目录执行 `build_solution_sbd.bat`。脚本会检查两个核级 SBD 的核心、器件和 FSP 版本，并根据 `solution.xml` 生成 `build/ra8p1_titan_dualcore.sbd`。该板级 SBD 用于 FSP 双核 solution 的分区与配置交换，不是可直接烧录的固件。
+
+RA8P1 的 Code MRAM 由两个核心共享，但 J-Link Flash Algorithm 需要通过 CPU0/AP0 访问，M33 调试则需要连接 CPU1/AP2。Keil 的一个 Target 只有一个 Device 选择，下载和调试共用该设置，因此无法在同一个 Target 中同时选择 CPU0 烧录和 CPU1 调试。两个 M33 Target 复用同一个 `Objects/template.axf`，并不是生成两份 M33 镜像。
+
+| Target | Device | 用途 |
+| --- | --- | --- |
+| `M33_Debug_CPU1` | `R7KA8P1KF:CPU1` | 编译 Cortex-M33 镜像并连接 CPU1；该 Target 的 Flash Download 功能已禁用。 |
+| `M33_Download_CPU0` | `R7KA8P1KF:CPU0` | 通过 Keil 原生 J-Link Flash 驱动和 CPU0，将已有 M33 AXF 烧写到 `0x020C0000`。 |
+
+在 `m33` 目录执行 `scons --target=mdk5` 可重新生成 `project.uvprojx`。两个 Target 都定义在 `template.uvprojx` 中，生成工程后仍会保留。
+
+1. 使用 `m85` Keil 工程编译并下载 CPU0 固件。
+2. 在 `m33` 工程中选择并编译 `M33_Debug_CPU1`。
+3. 切换到 `M33_Download_CPU0`，不要编译该 Target，直接点击 Download；J-Link 日志必须显示 `R7KA8P1KF_CPU0`。
+4. 烧录完成后切回 `M33_Debug_CPU1`，连接 CPU1 调试。
+
+启用 `BSP_START_SECONDARY_CORE` 后，CPU0 会在 `bsp/renesas/libraries/HAL_Drivers/drv_common.c` 的 RA 公共板级初始化中启动一次 CPU1，`hal_entry()` 不应再次启动 CPU1。
+
+不要在 M33 工程中执行 Reset。需要重启时按开发板复位键同时复位两个核，等待 M85 再次启动 CPU1 后重新 attach。
 
 **查看运行结果**
 
@@ -207,17 +236,17 @@ void hal_entry(void)
 
 选择左上角 file->open 打开配置文件
 
-![image-20251030163423452](figures/image-20251030163423452.png)
+![image-20251030163423452](m85/figures/image-20251030163423452.png)
 
 * **生成 FSP 代码：**
 
-![image-20251030163707813](figures/image-20251030163707813.png)
+![image-20251030163707813](m85/figures/image-20251030163707813.png)
 
 **RT-Thread Settings**
 
 在 RT-Thread Settings 中可以对 RT-Thread 的内核、组件、软件包以及 Titan Board 的设备驱动进行配置。
 
-![image-20250819173700386](figures/image-20250819173700386.png)
+![image-20250819173700386](m85/figures/image-20250819173700386.png)
 
 ## 联系人信息
 

bsp/renesas/ra8p1-titan-board/build_solution_sbd.bat

@@ -0,0 +1,37 @@
+@echo off
+setlocal ENABLEEXTENSIONS ENABLEDELAYEDEXPANSION
+
+set "BspRoot=%~dp0"
+set "Cpu0Bundle=%BspRoot%m85\Objects\template.sbd"
+set "Cpu1Bundle=%BspRoot%m33\Objects\template.sbd"
+set "RascVersionFile=%BspRoot%m85\rasc_version.txt"
+
+if not exist "%Cpu0Bundle%" (
+    echo [ERROR] CPU0 Smart Bundle "%Cpu0Bundle%" does not exist.
+    echo [ERROR] Build the m85 Keil project first.
+    exit /b 1
+)
+
+if not exist "%Cpu1Bundle%" (
+    echo [ERROR] CPU1 Smart Bundle "%Cpu1Bundle%" does not exist.
+    echo [ERROR] Build the m33 Keil project first.
+    exit /b 1
+)
+
+call "%BspRoot%m85\rasc_version.bat" "%RascVersionFile%"
+if errorlevel 1 exit /b 1
+
+set /a idx=0
+for /f "usebackq tokens=*" %%a in ("%RascVersionFile%") do (
+    if !idx! EQU 2 set "RascExe=%%a"
+    set /a idx+=1
+)
+
+if not defined RascExe (
+    echo [ERROR] RASC executable is not configured.
+    exit /b 1
+)
+
+set "RascExe=%RascExe:rasc.exe=rascc.exe%"
+powershell -NoProfile -ExecutionPolicy Bypass -File "%BspRoot%build_solution_sbd.ps1" -RascExe "%RascExe%"
+exit /b %errorlevel%