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@RVECE-A-RISC-V-Community

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SudeepJoshi22/README.md
  • 👋 Hi, I’m @SudeepJoshi22
  • 👀 I’m interested in ... Computer Architecture, VLSI, Embedded Systems, DSP and Amateur Astronomy
  • 🌱 I’m currently learning ... RISC-V ISA, Superscalar Architecture
  • 💞️ I’m looking to collaborate on ... RISC-V CPU, AI Hardware and DSP projects
  • 📫 How to reach me ... follow me on Linkedin: https://www.linkedin.com/in/sudeep-joshi-569951207/

Popular repositories Loading

  1. Minor-Project-2023-RISC-V-processor Minor-Project-2023-RISC-V-processor Public

    Verilog HDL code and documentation for pipelined RISC-V processors designed as a minor project by a team of 4. Includes testbench files, documentation, and sample programs. Completed as part of our…

    Verilog 11 1

  2. DHRUT-V DHRUT-V Public

    DHRUT-V :- In-order superscalar RV32I RISC-V processor core written in SystemVerilog and Verified using cocotb+pyUVM. Built for education, verification, and hardware exploration. (Can it run Doom? …

    Verilog 9 2

  3. CORDIC-Unit CORDIC-Unit Public

    CORDIC Unit designed in Verilog HDL. Completely reconfigurable with the number of iterations and Qm.n format

    Verilog 4 1

  4. Small_Projects Small_Projects Public

    C 1

  5. FFT_HARDWARE FFT_HARDWARE Public

    FFT Hardware written in TL-Verilog.

    Verilog 1

  6. cocotb-tutorial cocotb-tutorial Public

    Learning Cocotb

    Python 1