variables: VERILOG_TOP_PARAMS yaml gaffe

[oharboe]

[oharboe]

@tspyrou @maliberty @povik @MrAMS Pareto front for area, compute/time, compute/energy using synthesis parameters. In reality we're using Chisel instead of SystemVerilog parameters, but I think SystemVerilog parameters broadens the audience and allows for faster turnaround times when solving all the various and sundry niggling little issues with such a DSE.

https://github.com/The-OpenROAD-Project/bazel-orfs/tree/main/optuna

Interactive 3d graph pareto front

My goal here is to have a public test case that I can refer to for collaboration and test cases, my goal here isn't a polished example as such.

[maliberty]

conflicts to resolve