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6 changes: 4 additions & 2 deletions docs/user/FlowVariables.md
Original file line number Diff line number Diff line change
Expand Up @@ -140,6 +140,7 @@ configuration file.
| <a name="DISABLE_VIA_GEN"></a>DISABLE_VIA_GEN| Passed as -disable_via_gen to detailed_route.| |
| <a name="DONT_BUFFER_PORTS"></a>DONT_BUFFER_PORTS| Do not buffer input/output ports during floorplanning.| 0|
| <a name="DONT_USE_CELLS"></a>DONT_USE_CELLS| Dont use cells eases pin access in detailed routing.| |
| <a name="DPL_USE_OLD_DIAMOND"></a>DPL_USE_OLD_DIAMOND| Use the former diamond search legalizer for detailed placement instead of the default negotiation legalizer.| 0|
| <a name="DPO_MAX_DISPLACEMENT"></a>DPO_MAX_DISPLACEMENT| Specifies how far an instance can be moved when optimizing.| 5 1|
| <a name="EARLY_SIZING_CAP_RATIO"></a>EARLY_SIZING_CAP_RATIO| Ratio between the input pin capacitance and the output pin load during initial gate sizing.| |
| <a name="ENABLE_DPO"></a>ENABLE_DPO| Enable detail placement with improve_placement feature.| 1|
Expand Down Expand Up @@ -321,7 +322,6 @@ configuration file.
| <a name="TNS_END_PERCENT"></a>TNS_END_PERCENT| Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all violating endpoints by default (reduce to 5% for runtime). Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed.| 100|
| <a name="UNSET_ABC9_BOX_CELLS"></a>UNSET_ABC9_BOX_CELLS| List of cells to unset the abc9_box attribute on| |
| <a name="USE_FILL"></a>USE_FILL| Whether to perform metal density filling.| 0|
| <a name="USE_NEGOTIATION"></a>USE_NEGOTIATION| Enable using negotiation legalizer for detailed placement.| 0|
| <a name="VERILOG_DEFINES"></a>VERILOG_DEFINES| Preprocessor defines passed to the language frontend. Example: `-D HPDCACHE_ASSERT_OFF`| |
| <a name="VERILOG_FILES"></a>VERILOG_FILES| The path to the design Verilog/SystemVerilog files providing a description of modules.| |
| <a name="VERILOG_INCLUDE_DIRS"></a>VERILOG_INCLUDE_DIRS| Specifies the include directories for the Verilog input files.| |
Expand Down Expand Up @@ -462,6 +462,7 @@ configuration file.
- [CLUSTER_FLOPS_ARGS](#CLUSTER_FLOPS_ARGS)
- [DETAIL_PLACEMENT_ARGS](#DETAIL_PLACEMENT_ARGS)
- [DONT_BUFFER_PORTS](#DONT_BUFFER_PORTS)
- [DPL_USE_OLD_DIAMOND](#DPL_USE_OLD_DIAMOND)
- [EARLY_SIZING_CAP_RATIO](#EARLY_SIZING_CAP_RATIO)
- [FLOORPLAN_DEF](#FLOORPLAN_DEF)
- [GLOBAL_PLACEMENT_ARGS](#GLOBAL_PLACEMENT_ARGS)
Expand Down Expand Up @@ -507,6 +508,7 @@ configuration file.
- [CTS_SNAPSHOT](#CTS_SNAPSHOT)
- [CTS_SNAPSHOTS](#CTS_SNAPSHOTS)
- [DETAILED_METRICS](#DETAILED_METRICS)
- [DPL_USE_OLD_DIAMOND](#DPL_USE_OLD_DIAMOND)
- [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN)
- [LEC_AUX_VERILOG_FILES](#LEC_AUX_VERILOG_FILES)
- [LEC_CHECK](#LEC_CHECK)
Expand All @@ -531,6 +533,7 @@ configuration file.

- [CELL_PAD_IN_SITES_DETAIL_PLACEMENT](#CELL_PAD_IN_SITES_DETAIL_PLACEMENT)
- [DETAILED_METRICS](#DETAILED_METRICS)
- [DPL_USE_OLD_DIAMOND](#DPL_USE_OLD_DIAMOND)
- [ENABLE_RESISTANCE_AWARE](#ENABLE_RESISTANCE_AWARE)
- [GLOBAL_ROUTE_ARGS](#GLOBAL_ROUTE_ARGS)
- [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN)
Expand Down Expand Up @@ -660,5 +663,4 @@ configuration file.
- [TAP_CELL_NAME](#TAP_CELL_NAME)
- [TECH_LEF](#TECH_LEF)
- [USE_FILL](#USE_FILL)
- [USE_NEGOTIATION](#USE_NEGOTIATION)

10 changes: 5 additions & 5 deletions flow/designs/asap7/gcd-ccs/rules-base.json
Original file line number Diff line number Diff line change
Expand Up @@ -28,11 +28,11 @@
"compare": "<="
},
"cts__timing__setup__ws": {
"value": -63.5,
"value": -63.4,
"compare": ">="
},
"cts__timing__setup__tns": {
"value": -773.0,
"value": -768.0,
"compare": ">="
},
"cts__timing__hold__ws": {
Expand All @@ -48,11 +48,11 @@
"compare": "<="
},
"globalroute__timing__setup__ws": {
"value": -63.5,
"value": -63.4,
"compare": ">="
},
"globalroute__timing__setup__tns": {
"value": -771.0,
"value": -766.0,
"compare": ">="
},
"globalroute__timing__hold__ws": {
Expand Down Expand Up @@ -84,7 +84,7 @@
"compare": ">="
},
"finish__timing__setup__tns": {
"value": -1270.0,
"value": -1430.0,
"compare": ">="
},
"finish__timing__hold__ws": {
Expand Down
6 changes: 3 additions & 3 deletions flow/designs/asap7/gcd/rules-base.json
Original file line number Diff line number Diff line change
Expand Up @@ -52,7 +52,7 @@
"compare": ">="
},
"globalroute__timing__setup__tns": {
"value": -1790.0,
"value": -2050.0,
"compare": ">="
},
"globalroute__timing__hold__ws": {
Expand All @@ -64,7 +64,7 @@
"compare": ">="
},
"detailedroute__route__wirelength": {
"value": 1324,
"value": 1947,
"compare": "<="
},
"detailedroute__route__drc_errors": {
Expand All @@ -84,7 +84,7 @@
"compare": ">="
},
"finish__timing__setup__tns": {
"value": -1570.0,
"value": -1820.0,
"compare": ">="
},
"finish__timing__hold__ws": {
Expand Down
4 changes: 2 additions & 2 deletions flow/designs/asap7/ibex/rules-base.json
Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@
"compare": ">="
},
"cts__timing__setup__tns": {
"value": -1630.0,
"value": -13700.0,
"compare": ">="
},
"cts__timing__hold__ws": {
Expand Down Expand Up @@ -96,7 +96,7 @@
"compare": ">="
},
"finish__design__instance__area": {
"value": 2816,
"value": 2810,
"compare": "<="
}
}
6 changes: 3 additions & 3 deletions flow/designs/asap7/riscv32i-mock-sram/rules-base.json
Original file line number Diff line number Diff line change
Expand Up @@ -48,11 +48,11 @@
"compare": "<="
},
"globalroute__timing__setup__ws": {
"value": -56.5,
"value": -47.5,
"compare": ">="
},
"globalroute__timing__setup__tns": {
"value": -407.0,
"value": -190.0,
"compare": ">="
},
"globalroute__timing__hold__ws": {
Expand Down Expand Up @@ -84,7 +84,7 @@
"compare": ">="
},
"finish__timing__setup__tns": {
"value": -298.0,
"value": -1330.0,
"compare": ">="
},
"finish__timing__hold__ws": {
Expand Down
6 changes: 3 additions & 3 deletions flow/designs/asap7/uart/rules-base.json
Original file line number Diff line number Diff line change
Expand Up @@ -64,7 +64,7 @@
"compare": ">="
},
"detailedroute__route__wirelength": {
"value": 1673,
"value": 1973,
"compare": "<="
},
"detailedroute__route__drc_errors": {
Expand All @@ -80,11 +80,11 @@
"compare": "<="
},
"finish__timing__setup__ws": {
"value": -52.4,
"value": -47.3,
"compare": ">="
},
"finish__timing__setup__tns": {
"value": -1320.0,
"value": -1210.0,
"compare": ">="
},
"finish__timing__hold__ws": {
Expand Down
4 changes: 2 additions & 2 deletions flow/designs/gf180/ibex/rules-base.json
Original file line number Diff line number Diff line change
Expand Up @@ -84,7 +84,7 @@
"compare": ">="
},
"finish__timing__setup__tns": {
"value": -2.22,
"value": -4.76,
"compare": ">="
},
"finish__timing__hold__ws": {
Expand All @@ -96,7 +96,7 @@
"compare": ">="
},
"finish__design__instance__area": {
"value": 764974,
"value": 764104,
"compare": "<="
}
}
2 changes: 1 addition & 1 deletion flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json
Original file line number Diff line number Diff line change
Expand Up @@ -64,7 +64,7 @@
"compare": ">="
},
"detailedroute__route__wirelength": {
"value": 37489,
"value": 44583,
"compare": "<="
},
"detailedroute__route__drc_errors": {
Expand Down
6 changes: 3 additions & 3 deletions flow/designs/ihp-sg13g2/ibex/rules-base.json
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
{
"synth__design__instance__area__stdcell": {
"value": 280000.0,
"value": 278000.0,
"compare": "<="
},
"constraints__clocks__count": {
Expand All @@ -12,7 +12,7 @@
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
"value": 20659,
"value": 20256,
"compare": "<="
},
"detailedplace__design__violations": {
Expand Down Expand Up @@ -64,7 +64,7 @@
"compare": ">="
},
"detailedroute__route__wirelength": {
"value": 895142,
"value": 1137972,
"compare": "<="
},
"detailedroute__route__drc_errors": {
Expand Down
2 changes: 1 addition & 1 deletion flow/designs/ihp-sg13g2/spi/rules-base.json
Original file line number Diff line number Diff line change
Expand Up @@ -64,7 +64,7 @@
"compare": ">="
},
"detailedroute__route__wirelength": {
"value": 3972,
"value": 4623,
"compare": "<="
},
"detailedroute__route__drc_errors": {
Expand Down
10 changes: 5 additions & 5 deletions flow/designs/nangate45/ariane133/rules-base.json
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
"compare": "=="
},
"placeopt__design__instance__area": {
"value": 827643,
"value": 827361,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
Expand All @@ -32,7 +32,7 @@
"compare": ">="
},
"cts__timing__setup__tns": {
"value": -502.0,
"value": -556.0,
"compare": ">="
},
"cts__timing__hold__ws": {
Expand All @@ -52,7 +52,7 @@
"compare": ">="
},
"globalroute__timing__setup__tns": {
"value": -556.0,
"value": -642.0,
"compare": ">="
},
"globalroute__timing__hold__ws": {
Expand Down Expand Up @@ -84,7 +84,7 @@
"compare": ">="
},
"finish__timing__setup__tns": {
"value": -549.0,
"value": -604.0,
"compare": ">="
},
"finish__timing__hold__ws": {
Expand All @@ -96,7 +96,7 @@
"compare": ">="
},
"finish__design__instance__area": {
"value": 837050,
"value": 836289,
"compare": "<="
}
}
4 changes: 2 additions & 2 deletions flow/designs/nangate45/bp_fe_top/rules-base.json
Original file line number Diff line number Diff line change
Expand Up @@ -80,11 +80,11 @@
"compare": "<="
},
"finish__timing__setup__ws": {
"value": -0.15,
"value": -0.14,
"compare": ">="
},
"finish__timing__setup__tns": {
"value": -1.58,
"value": -1.95,
"compare": ">="
},
"finish__timing__hold__ws": {
Expand Down
16 changes: 8 additions & 8 deletions flow/designs/nangate45/jpeg/rules-base.json
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
{
"synth__design__instance__area__stdcell": {
"value": 102000.0,
"value": 99800.0,
"compare": "<="
},
"constraints__clocks__count": {
Expand All @@ -12,27 +12,27 @@
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
"value": 68509,
"value": 68139,
"compare": "<="
},
"detailedplace__design__violations": {
"value": 0,
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
"value": 5957,
"value": 5925,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
"value": 5957,
"value": 5925,
"compare": "<="
},
"cts__timing__setup__ws": {
"value": -0.139,
"compare": ">="
},
"cts__timing__setup__tns": {
"value": -54.6,
"value": -43.0,
"compare": ">="
},
"cts__timing__hold__ws": {
Expand All @@ -52,7 +52,7 @@
"compare": ">="
},
"globalroute__timing__setup__tns": {
"value": -66.5,
"value": -52.7,
"compare": ">="
},
"globalroute__timing__hold__ws": {
Expand All @@ -64,7 +64,7 @@
"compare": ">="
},
"detailedroute__route__wirelength": {
"value": 631144,
"value": 767282,
"compare": "<="
},
"detailedroute__route__drc_errors": {
Expand All @@ -84,7 +84,7 @@
"compare": ">="
},
"finish__timing__setup__tns": {
"value": -53.3,
"value": -46.7,
"compare": ">="
},
"finish__timing__hold__ws": {
Expand Down
4 changes: 2 additions & 2 deletions flow/designs/nangate45/mempool_group/rules-base.json
Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@
"compare": ">="
},
"cts__timing__setup__tns": {
"value": -12000.0,
"value": -12100.0,
"compare": ">="
},
"cts__timing__hold__ws": {
Expand All @@ -52,7 +52,7 @@
"compare": ">="
},
"globalroute__timing__setup__tns": {
"value": -14000.0,
"value": -12100.0,
"compare": ">="
},
"globalroute__timing__hold__ws": {
Expand Down
2 changes: 1 addition & 1 deletion flow/designs/nangate45/swerv/config.mk
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@ export PLATFORM = nangate45
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/swerv_wrapper.sv2v.v
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc

export CORE_UTILIZATION = 65
export CORE_UTILIZATION = 64
export CORE_ASPECT_RATIO = 1
export CORE_MARGIN = 5

Expand Down
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