Add RISC-V Zvbc vector CRC32C acceleration

[Felix-Gong]

Summary

• Implement CRC32C using RISC-V Zvbc vector carry-less multiplication (vclmul/vclmulh RVV intrinsics)
• Processes 4 lanes of 128-bit folding per iteration (64 bytes), with 4-to-1 lane reduction and Barrett reduction
• Add WITH_RISCV_ZVBC cmake option
• Zvbc preferred over Zbc in Choose_Extend() for higher throughput

Background

This extends the existing Zbc scalar CRC32C optimization (merged in #3312) with vector support. The implementation follows the same 128-bit folding + Barrett reduction approach used in x86 SSE4.2 and ARM PMULL.

Key implementation details

• With VLEN=128, each vector register holds 2×64-bit elements, so 2 vector register pairs = 128-bit lane
• Fold constants: k1=0x740eef02 (x^256 mod P), k2=0x9e4addf8 (x^320 mod P), k3=0xf20c0dfe (x^128 mod P), k4=0x493c7d27 (x^192 mod P)
• Cross-element XOR via scalar extraction (practical for VLEN=128 with only 2 elements)
• Barrett reduction uses scalar clmul/clmulh (Zbc instructions, available when Zvbc is present)

Testing

Verified on QEMU with -cpu rv64,zvbc=true,v=true,vlen=128:

• All RFC 3720 B.4 test vectors pass
• Large data (64/128/256/1024 bytes) results match x86 SSE4.2 reference values
• Extend (chained CRC) works correctly
• Zvbc and Zbc paths produce identical results

Build

cmake -DWITH_RISCV_ZVBC=ON ..