pulley/cranelift: opcode fusion at call_indirect lazy-init dispatch tail

cranelift/codegen/meta/src/pulley.rs

@@ -97,6 +97,13 @@ impl Inst<'_> {
             // Skip special instructions not used in Cranelift.
             "XPush32Many" | "XPush64Many" | "XPop32Many" | "XPop64Many" => true,
 
+            // Phase-3 fused dispatch op: 3 writable results would
+            // require extending the auto-codegen `results[..]` match
+            // arms below. The op is emitted only via the hand-written
+            // `MInst::BandFuncrefDispatch` path, so no auto-generated
+            // ISLE rule is needed — skip here.
+            n if n.starts_with("XbandFuncrefDispatch") => true,
+
             // Skip more branching-related instructions.
             n => n.starts_with("Br"),
         }

cranelift/codegen/src/isa/pulley_shared/inst.isle

@@ -67,6 +67,48 @@
     ;; Jump to `then` if `c` is true, otherwise to `else`.
     (BrIf (cond Cond) (taken MachLabel) (not_taken MachLabel))
 
+    ;; Fused `band src, mask` + `brif src` emitted at the call_indirect
+    ;; lazy-init brif site. `dst = src & sign_extend(mask)` is
+    ;; unconditional; the branch test is on `src`'s low-32 or full-64 bits
+    ;; per `size`. Pulley-side: `xband*_s8_br_if_*`.
+    (BandBrIf
+      (dst WritableXReg)
+      (src XReg)
+      (mask i8)
+      (size OperandSize)
+      (taken MachLabel)
+      (not_taken MachLabel))
+
+    ;; Funcref-dispatch fusion: `brif (band v -2) + load code + load vmctx`
+    ;; across the brif and its continuation block. Emitted at the
+    ;; call_indirect lazy-init site under
+    ;; `is_eagerly_initialized_funcref_table`. Pulley-side:
+    ;; `xfuncref_dispatch_{x64,not_x64,x32,not_x32}`.
+    (FuncrefDispatch
+      (dst_code WritableXReg)
+      (dst_vmctx WritableXReg)
+      (src XReg)
+      (offset_code i8)
+      (offset_vmctx i8)
+      (size OperandSize)
+      (taken MachLabel)
+      (not_taken MachLabel))
+
+    ;; FuncrefDispatch + the preceding `xband_s8 -2` absorbed. `src` is
+    ;; the unmasked funcref; the fused op writes `dst_masked = src & -2`
+    ;; so the brif's block-call-arg copy still has a producer.
+    ;; Pulley-side: `xband_funcref_dispatch_{x64,not_x64,x32,not_x32}`.
+    (BandFuncrefDispatch
+      (dst_masked WritableXReg)
+      (dst_code WritableXReg)
+      (dst_vmctx WritableXReg)
+      (src XReg)
+      (offset_code i8)
+      (offset_vmctx i8)
+      (size OperandSize)
+      (taken MachLabel)
+      (not_taken MachLabel))
+
     ;; Load the memory address referenced by `mem` into `dst`.
     (LoadAddr (dst WritableXReg) (mem Amode))
 

cranelift/codegen/src/isa/pulley_shared/inst/args.rs

@@ -577,6 +577,19 @@ pub struct PulleyCall {
     pub args: SmallVec<[XReg; 4]>,
 }
 
+/// Payload of `CallInfo` for `Inst::IndirectCall`. Mirror of `PulleyCall`:
+/// the first 0–4 integer ABI args are tracked here so the emitted
+/// `call_indirect{1,2,3,4}` opcode moves them into `x0..x3` itself
+/// instead of regalloc synthesising `xmov`s. Remaining args use the
+/// fixed-preg path in `CallInfo::uses`.
+#[derive(Clone, Debug)]
+pub struct PulleyCallIndirect {
+    /// The register holding the call target.
+    pub target: XReg,
+    /// Up to 4 integer args destined for `x0..x3`.
+    pub args: SmallVec<[XReg; 4]>,
+}
+
 pub use super::super::lower::isle::generated_code::AddrO32;
 
 impl Copy for AddrO32 {}