v0.6.9

What's Changed

• Add automation for code coverage in pushes by @maifeeulasad in #646
• Improvement in naming to match a future converged solution by @desmonddak in #650
• Fixing tool installation order for report generation in coverage script (#646) by @maifeeulasad in #651
• Fix inOut unnamed loopback bug by @mkorbel1 in #655
• Preparing to release v0.6.9 by @mkorbel1 in #656

New Contributors

• @maifeeulasad made their first contribution in #646

Full Changelog: v0.6.8...v0.6.9

v0.6.8

What's Changed

• Fix typos by @antonkesy in #642
• Fix bug where const assignments could be lost in some disallowed const scenarios by @mkorbel1 in #643
• Fix bug where output/inOut connection is incorrectly pruned when unnamed by @mkorbel1 in #644
• Preparing to release v0.6.8 by @mkorbel1 in #645

New Contributors

• @antonkesy made their first contribution in #642

Full Changelog: v0.6.7...v0.6.8

v0.6.7

What's Changed

• LogicValue.ofRadixString returning 0 on bad input instead of throwing by @desmonddak in #617
• Deprecate PairInterface.modify in favor of uniquify on addSubInterface by @mkorbel1 in #620
• fixes for pub.dev issues in 0.6.6 by @desmonddak in #621
• Performance optimization on Conditional.driveX by @mkorbel1 in #623
• Improve WriteAfterReadException message with trace of involved assignments by @mkorbel1 in #624
• Fix typo in user guide by @gharbi-mohamed-dev in #626
• Improve exceptions for SSA checks with improper reuse by @mkorbel1 in #625
• Driving and receiving of hierarchical PairInterfaces by @mkorbel1 in #628
• Fix bug where one-bit struct output ports improperly slice by @mkorbel1 in #629
• Fix bug where cached packed on LogicStructures on output ports reused inside and out cause build trace failures by @mkorbel1 in #631
• Fix bug with Module port naming in generated outputs when LogicStructures contain ports by @mkorbel1 in #630
• Improve SSA error debuggability with hierarchy by @mkorbel1 in #635
• Fix bug where partial array assignments could cause missing assignments in generated outputs by @mkorbel1 in #637
• Mark bit ranges of swizzles with comments in generated SystemVerilog by @mkorbel1 in #627
• Pruning, empty disconnected ports, and removal of unused signals by @mkorbel1 in #638
• Preparing to release v0.6.7 by @mkorbel1 in #640

New Contributors

• @gharbi-mohamed-dev made their first contribution in #626

Full Changelog: v0.6.6...v0.6.7

v0.6.6

What's Changed

• Fixing selecting the module and reflecting the respective signal table by @aneriach in #612
• Cloning and matching by @mkorbel1 in #614
• Preparing to release v0.6.6 by @mkorbel1 in #618

New Contributors

• @aneriach made their first contribution in #612

Full Changelog: v0.6.5...v0.6.6

v0.6.5

What's Changed

• bug fix for zero value toRadixString() by @desmonddak in #606
• Preparing to release v0.6.5 by @mkorbel1 in #607

Full Changelog: v0.6.4...v0.6.5

v0.6.4

What's Changed

• Fix bug in LogicStructure.previousValue by @mkorbel1 in #565
• Deprecate Port and move to Logic.port for API consistency by @lucasphillips in #575
• Add documentation and example code for selectIndex and selectFrom by @laeticiachee in #576
• Fix bug in cross-stage accesses in Pipeline by @mkorbel1 in #588
• Enhance LogicValue.toRadixString to enable fixed-width output by @desmonddak in #583
• FiniteStateMachine upgrades by @mkorbel1 in #593
• Modularity and improvements for Synth infrastructure by @mkorbel1 in #598
• Fix memory leak in combinational guarding by @mkorbel1 in #602
• Preparing to release v0.6.4 by @mkorbel1 in #603

New Contributors

• @lucasphillips made their first contribution in #575
• @laeticiachee made their first contribution in #576

Full Changelog: v0.6.3...v0.6.4

v0.6.3

What's Changed

• Bug fix for withSet in LogicStructure. by @kimmeljo in #561
• Fix bug where non-async flop generates async flop by @mkorbel1 in #564
• Rohd Devtools Extension Refactor to BLoC by @robtorx in #562
• Preparing to release v0.6.3 by @mkorbel1 in #563

New Contributors

• @robtorx made their first contribution in #562

Full Changelog: v0.6.2...v0.6.3

v0.6.2

What's Changed

• Transition to using a different addition syntax for lint avoidance by @mkorbel1 in #478
• Simulator end of sim actions and exception handling by @mkorbel1 in #558
• Support VCDs generated by Verilator in VcdParser by @mkorbel1 in #557
• Preparing to release v0.6.2 by @mkorbel1 in #560

Full Changelog: v0.6.1...v0.6.2

v0.6.1

What's Changed

• Fix bug in SSA discovery when LogicStructures are used by @mkorbel1 in #540
• Fix bug where Module.build didn't follow through structs containing ports properly, plus improved debug messaging. by @mkorbel1 in #541
• fix radix10 issue in toRadixString by @desmonddak in #543
• Add Logic.named and broaden clone by @mkorbel1 in #550
• Preparing to release v0.6.1 by @mkorbel1 in #555

Full Changelog: v0.6.0...v0.6.1

v0.6.0

What's Changed

• LogicNets, inOuts, and TriStateBuffer (support for bidirectional wires) by @mkorbel1 in #485
• Improve simulator timestamp in past errors, suggest reset, fix #490 by @mkorbel1 in #491
• RTL to have one array-array assignment instead of bit blasted assignments by @sshankar4 in #487
• Performance fixes: wrong collections and unmodifiable views causing inefficiencies by @mkorbel1 in #492
• Update analysis options, lint cleanup, SDK workaround removal by @mkorbel1 in #495
• Fix bug in internal array discovery during Module build by @mkorbel1 in #494
• Fix bug where unconnected array drivers may be omitted incorrectly by @mkorbel1 in #496
• Add support for SystemVerilog parameter passthroughs by @mkorbel1 in #497
• Do not generate SystemVerilog parameter syntax when there are 0 parameters by @mkorbel1 in #498
• Fix bug in LogicStructure.getRange calculations by @mkorbel1 in #499
• Logic.assignSubset for partial assignments to Logic by @mkorbel1 in #502
• Add inputSource and inOutSource to Module by @mkorbel1 in #503
• Bug fix: shuffled array assignments incorrectly collapsed in generated SV by @mkorbel1 in #504
• Upgrade and improve Uniquifier API by @mkorbel1 in #505
• Improved port already exists error message with module name by @c0d3-br3ak9r in #526
• Doc fixes and a couple more tests by @mkorbel1 in #525
• RadixString code by @desmonddak in #529
• Allow LogicNets to bidirectionally drive operations which are just wires by @mkorbel1 in #532
• Async Reset Improvements by @mkorbel1 in #533
• Fix bugs in Simulator error handling and end of simulation by @mkorbel1 in #515
• LogicValue radixString uses underscore separators by default by @desmonddak in #535
• Improvements to asynchronous trigger and injection handling by @mkorbel1 in #537
• Documentation and miscellaneous minor cleanup by @mkorbel1 in #538
• Preparing to release v0.6.0 by @mkorbel1 in #539

New Contributors

• @sshankar4 made their first contribution in #487
• @c0d3-br3ak9r made their first contribution in #526
• @desmonddak made their first contribution in #529

Full Changelog: v0.5.3...v0.6.0