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1. SiliconForge-Security-SoC SiliconForge-Security-SoC Public

   芯片安全认证系统：RO-PUF物理指纹+Bio-Hash身份验证+异常检测FSM

   Verilog 3

2. -3D-Physical-Lock-Global-Logic-Licensing-Whitepaper-V2.0- -3D-Physical-Lock-Global-Logic-Licensing-Whitepaper-V2.0- Public

3. CSL-LLM-Architecture CSL-LLM-Architecture Public

   Description: The official specification for Chip Simulation-to-Tapeout Large Language Model (CSL-LLM). Enabling physical sovereignty and hardware self-healing for 3nm/2nm nodes via the CTC System.

   Verilog 1