A couple of minor improvements and cleanliness work

[nathanaelhuffman]

We really want to assert UART backpressure before we're full. This adjusts down the almost full threshold. In practice, I don't believe that we'd ever actually end up filling the rx FIFO here b/c it just bleeds immediately into the much bigger (4kB) IPCC fifo in the eSPI block, but for correctness I think this is a solid change.

I also adjusted where we do the available bytes resizing for clarity. eSPI generally only allocates 12 bits for transfers, but we have a 4kB fifo so 13bits are required to represent a completely full FIFO. I moved the resize over to where we're stuffing eSPI packets, where we're already doing a minimum(bytes_in_fifo, 61) so we'll never send more than 61. We also never see a full IPCC FIFO in practice so I think none of this ends up being a functional change.