[executorch][cuda] Optimize short-query INT6 matvec kernels

[Gasoonjia]

Stack from ghstack (oldest at bottom):

• [executorch][cuda] Optimize short-query INT5 matvec kernels #21475
• -> [executorch][cuda] Optimize short-query INT6 matvec kernels #21474
• [executorch][cuda] Optimize short-query INT4 matvec kernels #21473

Add compile-time M=1/2/3/4 short-query paths and share their safe implementation through a ROWS/USE_SUM/GS16 device template. These kernels were generated and tuned with KernelAgent. Dispatch uses the regular gs16 kernels for M=1/2 and the precomputed-activation-sum kernels for M=3/4. The M=3 non-sum entry remains explicit as a performance/correctness comparison because templating that entry increased register pressure.

A100 op-level results (N=6656, gs=16, three seeds):

• M1, generic reference -> gs16: 0.039416 -> 0.038211 ms (1.032x; no regression)
• M2, generic reference -> gs16: 0.055348 -> 0.032540 ms (1.701x)
• M3, optimized non-sum -> activation-sum: 0.040003 -> 0.039949 ms (1.001x; neutral incremental change)
• M4, generic reference -> activation-sum: 0.100204 -> 0.045694 ms (2.193x)

The M3 baseline is intentionally the optimized non-sum kernel rather than the generic reference; this isolates the activation-sum optimization. All candidates are bitwise-correct across the three seeds, and ptxas reports zero spills.

Differential Revision: D114032330

[pytorch-bot]

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