[executorch][cuda] Optimize short-query INT5 matvec kernels - #21475
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🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/21475
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Pull Request resolved: #21475 Add specialized M=1 and M=4 short-query paths for the planar INT5 W5A8 matvec operator. These are the latency-sensitive single-row and four-row shapes. M=2/M=3 retain the generic fallback path; this change does not claim those shapes as optimized. The M=1 implementation shares safe gs32 decode/accumulate logic through a compile-time ROWS device template. M=4 remains explicit because KernelAgent experiments with the generalized template increased register pressure and regressed latency. The final kernels were generated and tuned with KernelAgent. A100 kernel microbenchmarks versus the previous generic path: - M1: 1.09971 -> 0.70441 ms (1.56x; no regression) - M4: 1.96445 -> 1.12976 ms (1.74x) - M2/M3: no specialized dispatch; generic fallback remains unchanged Correctness tests cover M=1,2,3,4 with three randomized seeds; ptxas reports zero spills. ghstack-source-id: 408520032 @exported-using-ghexport Differential Revision: [D114032323](https://our.internmc.facebook.com/intern/diff/D114032323/)
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Add specialized M=1 and M=4 short-query paths for the planar INT5 W5A8 matvec operator. These are the latency-sensitive single-row and four-row shapes. M=2/M=3 retain the generic fallback path; this change does not claim those shapes as optimized.
The M=1 implementation shares safe gs32 decode/accumulate logic through a compile-time ROWS device template. M=4 remains explicit because KernelAgent experiments with the generalized template increased register pressure and regressed latency. The final kernels were generated and tuned with KernelAgent.
A100 kernel microbenchmarks versus the previous generic path:
Correctness tests cover M=1,2,3,4 with three randomized seeds; ptxas reports zero spills.
Differential Revision: D114032323